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1129 commits 39 branches 2 tags 15 MiB
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857 commits

Author SHA1 Message Date
Dolu1990
6aa6191240 Merge branch 'master' into dev 
# Conflicts:
#	build.sbt
#	src/main/scala/vexriscv/Riscv.scala
#	src/main/scala/vexriscv/ip/DataCache.scala
#	src/main/scala/vexriscv/plugin/DBusSimplePlugin.scala
#	src/main/scala/vexriscv/plugin/MmuPlugin.scala
#	src/test/cpp/regression/makefile
#	src/test/scala/vexriscv/TestIndividualFeatures.scala
 2021-01-30 20:30:21 +01:00
Dolu1990
d6e8a5ef22 VexRiscvSmpLitex options refractoring 2021-01-23 20:16:58 +01:00
Dolu1990
ce143e06f2 VexRiscvSmpLitex --in-order-decoder --wishbone-memory added 2021-01-23 17:48:34 +01:00
Dolu1990
bcd140fc42 Add vexRiscvConfig.withMmu option 2021-01-21 13:28:09 +01:00
Samuel Lindemer
6c13e6458f Remove registers storing PMP region bounds 2021-01-20 14:27:38 +01:00
Samuel Lindemer
828ea96006 PMP registers are now WARL 2021-01-20 09:27:35 +01:00
Dolu1990
04499c0b76 FPU sqrt functional 2021-01-14 18:33:24 +01:00
Dolu1990
85dd5dbf8e fpu div functional, sqrt wip 2021-01-14 15:56:56 +01:00
Samuel Lindemer
5e6c645461 Distinguish between page faults from MMU and access faults from PMP 2021-01-14 09:45:38 +01:00
Dolu1990
8761d0d9ee FpuCore can add/mul/fma/store/load 2021-01-13 18:28:26 +01:00
Dolu1990
6e0be6e18c Cfu add state index and cfu index 2021-01-11 13:44:04 +01:00
Dolu1990
930bdf9dda DataCache increase syncPendingMax to 32 and use a sync queue instead of async one 2021-01-04 10:59:21 +01:00
Dolu1990
780ad01ac0 Add AES-instruction support 2020-12-21 11:52:55 +01:00
Dolu1990
c59499ec03 typo 2020-12-11 14:13:33 +01:00
Dolu1990
eaff52b264 Add comments to the AesPlugin 2020-12-11 13:51:10 +01:00
Dolu1990
6da09967f8 Add comments to the AesPlugin 2020-12-11 13:46:55 +01:00
Samuel Lindemer
7d699dcc13 Remove PMP from MachineOs test defaults 2020-12-10 09:42:27 +01:00
Samuel Lindemer
f2ce2eab00 PMP plugin passes regression tests 2020-12-07 12:04:45 +01:00
Samuel Lindemer
763eebeeba Add TOR support, tests pass on GenZephyr 2020-12-04 17:13:31 +01:00
Samuel Lindemer
5cb5061d9b PMP passes test with GenZephyr, but pipeline flushes have been disabled 2020-12-03 17:29:31 +01:00
Dolu1990
9a6931a54c CfuPlugin improve writeback buffering 2020-12-03 16:21:52 +01:00
Samuel Lindemer
987de8fb6a Lock PMP address registers in golden model 2020-12-02 14:18:17 +01:00
Samuel Lindemer
14c39a0070 Merge remote-tracking branch 'upstream/master' into pmp 2020-12-02 14:08:32 +01:00
Samuel Lindemer
872aa19d83 Add PMP to golden model 2020-12-02 12:27:26 +01:00
Samuel Lindemer
d5b1a8f565 Add PMP test to regression suite 2020-12-01 18:38:06 +01:00
Dolu1990
45ff78d068 VexRiscvSmpClusterGen.dBusCmdMasterPipe option added 2020-12-01 13:51:10 +01:00
Samuel Lindemer
c5023ad973 Add PMP regression test 2020-12-01 09:10:24 +01:00
Samuel Lindemer
2d0ebf1ef5 Flush pipeline after PMP CSR writes 2020-11-25 15:38:34 +01:00
Dolu1990
e0ae46e794 Fix Csr ReadWrite interration with DBusCachedPlugin execute halt 
# Conflicts:
#	src/main/scala/vexriscv/plugin/CsrPlugin.scala
 2020-11-18 14:43:24 +01:00
Dolu1990
832218dbec DBusCachedPlugin increase pendingMax to 64 to hide memory latency when saving a full context 2020-11-16 12:38:29 +01:00
Dolu1990
ba523c627a Fix Csr ReadWrite interration with DBusCachedPlugin execute halt 2020-11-16 12:37:48 +01:00
Dolu1990
c1b0869c21 AesPlugin is now little endian 2020-11-12 15:07:27 +01:00
Dolu1990
1b2a2ebaca DBusCachedPlugin miss decoded aquire fix 2020-11-12 15:07:07 +01:00
Dolu1990
05e725174c AesPlugin added, work with dropbear encryption, seem ok for decryption (barmetal) 2020-11-02 17:14:52 +01:00
Dolu1990
9abe19317d RegFilePlugin.x0Init do less assumption on other plugin behaviour 2020-11-02 17:01:17 +01:00
Samuel Lindemer
97fe279f7b Enable PMP register lock 2020-10-29 13:37:21 +01:00
Dolu1990
dc9246715d Do not allow jtag ebreak outside machine mode 2020-10-28 13:00:16 +01:00
Dolu1990
4209dc2792 Fix CsrPlugin privilege crossing 2020-10-28 13:00:15 +01:00
Dolu1990
576e21d75d Do not allow jtag ebreak outside machine mode 2020-10-28 12:58:24 +01:00
Dolu1990
abebeaea1f Fix CsrPlugin privilege crossing 2020-10-28 12:57:20 +01:00
Samuel Lindemer
fc2c8a7c37 Initial commit of PMP plugin 2020-10-27 09:38:58 +01:00
Dolu1990
fe342c347c CfuBusParameter has now a few default values 2020-10-23 11:06:24 +02:00
Marcus Comstedt
6c8e97f825 Update big endian instruction encoding 
Between draft-20181101-ebe1ca4 and draft-20190622-6993896 of the
RISC-V Instruction Set Manual, the wording was changed from requiring
"natural endianness" of instruction parcels to require them to be
little endian.

Update the big endian instruction pipe to reflect the newer requirement.
 2020-10-20 18:05:31 +02:00
Dolu1990
4ece59385d DataCache split redo / refilling execute stage halt 2020-10-19 18:12:20 +02:00
Dolu1990
ec55187033 improve LightShifterPlugin arbitration halt timings 2020-10-09 11:37:48 +02:00
Dolu1990
bbaa0520c0
Fix UserInterruptPlugin interrupt enable 2020-10-09 10:45:23 +02:00
bunnie
72f85ef6c0 Merge remote-tracking branch 'origin/dev' into dev-asid 2020-10-04 19:53:29 +08:00
bunnie
65e6f6054b Add ASID field to SATP 
ASID field is missing from the SATP which causes compatibility
issues with Xous.

While this patch resolves the Xous issue, it has not been tested
on Linux.
 2020-10-04 15:34:58 +08:00
Dolu1990
98de02051e
Merge pull request #135 from zeldin/bigendian 
Add support for big endian byte ordering
 2020-10-01 16:43:00 +02:00
Dolu1990
3f5e771a5c dbus mmu access improvement 2020-09-17 22:06:29 +02:00