Charles Papon
1a36f2689d
#60 Fix software model. Forgot physical address for on RVC instruction
2019-03-30 11:24:29 +01:00
Charles Papon
29980016f3
#60 Fix instruction fetch exception PC by forcing LSB to be zero
2019-03-30 10:10:25 +01:00
Dolu1990
9fff419346
Better fix
2019-03-29 09:18:44 +01:00
Dolu1990
391cff69d3
#60 should fix the first instruction fetch privilege after interrupt
2019-03-29 09:02:44 +01:00
Dolu1990
0c48729611
Sync impact less changes (asfar i know)
2019-03-29 08:43:15 +01:00
Dolu1990
ad27007c3c
DBusSimplePlugin AHB bridge add hazard checking, pass tests
2019-03-28 11:41:49 +01:00
Dolu1990
53c05c31c7
IBusSimplePlugin AHB bridge fix, pass tests
2019-03-28 10:12:42 +01:00
Dolu1990
b0522cb491
Add AhbLite3 simulation config
2019-03-28 08:32:12 +01:00
Tom Verbeure
6038730e53
Merge branch 'master' of https://github.com/SpinalHDL/VexRiscv
2019-03-27 19:49:09 -07:00
Dolu1990
9ac4998478
Fix emulator nested exception redirection privilege
2019-03-28 00:38:38 +01:00
Dolu1990
ac06111163
Fix MMU MPRV, Fix emulator nested exception
2019-03-27 22:58:30 +01:00
Dolu1990
0bed511a6c
Fix cacheless LR/SC xtval, did some SRC/ADD_SUB/ALU redesign
2019-03-27 18:58:02 +01:00
Dolu1990
43c3922a3d
Add prerequired stuff
2019-03-27 10:55:20 +01:00
Dolu1990
f113946e66
Added a neutral LINUX_SOC for sim purposes
2019-03-27 10:53:41 +01:00
Dolu1990
b69c474fa2
#60 user space reached
...
/sbin/init: error while loading shared libraries: libm.so.6: cannot stat shared object: Error 38
2019-03-27 00:26:51 +01:00
Dolu1990
7a9f7c4fb9
Untested cacheless buses to AHB bridges
2019-03-26 16:30:53 +01:00
Dolu1990
94fc2c3ecf
Fix some models missmatch
...
Add more SBI
Add hardware LR/SC support in dbus cacheless
2019-03-26 01:25:18 +01:00
Dolu1990
1c3fd5c38b
Fix mprv and add it into the softare model
2019-03-25 12:03:32 +01:00
Dolu1990
1ec11dc03d
Fix mprv
2019-03-25 11:47:56 +01:00
Dolu1990
c34f5413a3
Add MMU MPRIV for easier machinemode emulation #60
2019-03-25 10:30:13 +01:00
Dolu1990
d63c6818df
Merge pull request #67 from tomverbeure/manual
...
Some minor updated to the manual
2019-03-25 02:07:42 +01:00
Dolu1990
9d55283b3b
Machine mode emulator
2019-03-25 02:00:19 +01:00
Tom Verbeure
3d5e941aef
Merge branch 'master' of https://github.com/SpinalHDL/VexRiscv
2019-03-24 23:56:23 +00:00
Dolu1990
e28702eb40
Add PlicCost test
2019-03-24 12:17:39 +01:00
Dolu1990
6c0608f0dd
#60
...
Add LitexSoC workspace / linux loading.
Need to emulate peripherals and adapte the kernel now.
Probably also need some machine mode emulation
Software time !
2019-03-24 10:52:56 +01:00
Dolu1990
d70f970b15
Merge pull request #66 from tomverbeure/IBusSimple_to_PipelinedMemoryBus
...
Add getPipelinedMemoryBusConfig()
2019-03-24 08:05:21 +01:00
Tom Verbeure
ea62fd0e16
Same thing for DBusSimpleBus.
2019-03-23 23:36:13 +00:00
Tom Verbeure
1afad4f240
Ignore vim backup files.
2019-03-23 22:34:22 +00:00
Tom Verbeure
95c3e436dc
Make toPipelinedMemoryBus() just like the other busses
2019-03-23 22:32:48 +00:00
Dolu1990
0656a49332
Make xtval more compliant
2019-03-23 20:12:36 +01:00
Dolu1990
7159237104
Fix csrrs/csrrc for xip registers
2019-03-23 18:11:26 +01:00
Dolu1990
505bff6f45
CSR Plugin now implement interruptions as specified in the spec
2019-03-23 12:56:04 +01:00
Dolu1990
3652ede130
Add mdeleg tests
2019-03-23 11:41:10 +01:00
Dolu1990
9139b4d269
Restore all tests
2019-03-22 18:03:35 +01:00
Dolu1990
597336b491
MMU sum/mxr tested and ok, all seem finen
2019-03-22 17:11:55 +01:00
Dolu1990
f7b793b7bf
Add SSTATUS.SUM/MXR feature, need testing
2019-03-22 15:49:36 +01:00
Dolu1990
e4cdc2397a
MMU pass all test, need to and SUM and MXR and it's all ok
2019-03-22 14:52:49 +01:00
Dolu1990
2b458fc642
Added MMU superpage support, pass MMU tests
2019-03-22 12:23:47 +01:00
Dolu1990
af2acbd46e
Got the new MMU design to pass simple tests #60
2019-03-22 01:10:17 +01:00
Tom Verbeure
59a2817e5c
Update DecoderSimplePlugin manual.
2019-03-21 05:53:27 +00:00
Tom Verbeure
3f5605f22e
Fix table.
2019-03-21 05:36:30 +00:00
Tom Verbeure
02a6312912
Update IBusCachedPlugin manual.
2019-03-21 05:34:15 +00:00
Tom Verbeure
b7ddd02fc6
IBusSimplePlugin README.
2019-03-21 05:17:07 +00:00
Dolu1990
ea56481ead
Add supervisor CSR in the riscv golden model
2019-03-20 23:26:08 +01:00
Dolu1990
7cbe399f1f
Fix some supervisor CSR access
2019-03-20 23:25:52 +01:00
Dolu1990
6f2e5a0eb7
goldenmodel Implement some of the supervisor CSR
2019-03-20 20:28:04 +01:00
Dolu1990
39b2803914
Fix some CsrPlugin flags issues
2019-03-20 20:27:47 +01:00
Dolu1990
6c2fe934fd
Bring changes and fixies from @kgugala @daveshah1. Thanks guys !
2019-03-20 16:27:35 +01:00
Dolu1990
130a69eeae
Pass regressions machinemode with CSR config including Supervisor
2019-03-20 14:14:59 +01:00
Dolu1990
d205f88fb8
riscv golden model and RTL pass all current regressions
...
add RVC into the linux config
2019-03-20 12:17:43 +01:00