Per default, the processing should occur with sys_clk and dw, instead of
the phy parameters since it's not that much larger and allows for easier
timing requirements. But on some fpgas saving the few gates could be desirable
On ecp5 `FullMemoryWE` leads to an increase of DP16KD block mem, while
it works better on Intel/Altera devices according to
6c3af746e2.
Simple solution: Make it configurable
Fixes a bug which would fill the TX return channel FIFO whenever the
SRAM Reader FSM is in the IDLE state. Instead, the FIFO should be
filled when the FSM reaches the END state, in which it will remain for
exactly a single clock cycle.
Fixes: 392414eef8 ("mac: Review Timestamping, simplify and...")
Signed-off-by: Leon Schuermann <leon@is.currently.online>
- Simplify names (timestamp_source --> timestamp, tx/tx_timestamp CSR/Layouts --> timestamp, etc...)
- Simplify the logic a bit.
- Use consistent names for FIFO between Writer and Reader (cmd_fifo and stat_fifo).
- Avoid stat_fifo on Reader when Timestamp is disabled.
- Use EventSourceLevel() on Reader only when Timestamp is enabled.
This implements optional packet timestamping based on a hardware
timestamp source for outgoing Ethernet packets, as required by
applications such as IEEE 1588 (Precision Time Protocol).
This changes the liteeth SRAM reader to utilize a feedback channel
returning the slot of which a packet has been sent.
The event source is changed from a pulse to a level-based trigger,
such that it will continue asserted if a single packet has been
acknowledged, but additional packets have been sent.
This infrastructure allows to convey additional information about
transmitted packets, such as timestamps or errors.
This implements optional packet timestamping based on a hardware
timestamp source for incoming Ethernet packets, as required by
applications such as IEEE 1588 (Precision Time Protocol).
When a timestamp source is given as an argument, an additonal CSR is
generated containing the packet timestamp.
Background:
When there is a lot of broadcasts in the network, receive buffers
may overflow easly. Especially having onlu 2 of them.
To prevent that you can enlarge nrxslots, but because
nrxslots + ntxslots must be the power of two, you must also
inrease ntxslots. But there is no need to have more than 2 tx
buffers (they work as ping-pong buffer), the CPU will not use
more than two buffers.
So being able to set for example nrxslots=8 and ntxslots=2
is quite reasonable.
In some hardware, ref_clk can be input for both the MAC and the PHY. In this
case, setting refclk_cd to None will make the CRG use ref_clk as the RMII
input reference clock:
Pads:
# RMII Ethernet
("eth_clocks", 0,
Subsignal("ref_clk", Pins("D17")),
IOStandard("LVCMOS33"),
),
("eth", 0,
Subsignal("rst_n", Pins("F16")),
Subsignal("rx_data", Pins("A20 B18")),
Subsignal("crs_dv", Pins("C20")),
Subsignal("tx_en", Pins("A19")),
Subsignal("tx_data", Pins("C18 C19")),
Subsignal("mdc", Pins("F14")),
Subsignal("mdio", Pins("F13")),
Subsignal("rx_er", Pins("B20")),
Subsignal("int_n", Pins("D21")),
IOStandard("LVCMOS33")
),
PHY:
self.submodules.ethphy = LiteEthPHYRMII(
clock_pads = self.platform.request("eth_clocks"),
pads = self.platform.request("eth"),
refclk_cd = None)
Thanks @mwick83 for reporting the use case and for the initial implementation.
David Sawatzke
enjoy-digital
Anton Blanchard
Leon Schuermann
Jędrzej Boczar
Shawn Hoffman
Marek Czerski
Joel Stanley