92c30489ae
examples: use CRG from litex.build.
2020-04-10 10:31:14 +02:00
3bd807cf8f
litex.build: update from migen.genlib.io litex.build.io.
2020-04-10 09:20:41 +02:00
6ec7038b5b
.travis.yml: fix git clone error.
2020-04-07 12:16:37 +02:00
47a2e5b6fd
setup.py: simplify, switch to Python3.6+ (using python_requires), remove version.
...
- Deprecate Python 3.5, switch to Python 3.6+.
- Remove which was not used or updated. We'll see to get this back when working on releases.
2020-04-07 11:54:31 +02:00
ab55304ab7
mac/sram: use reset_less on datapath/configuration CSRStorages.
2020-04-06 13:17:30 +02:00
fb478537e7
phy/gmii: use a BUFG between eth_rx.clk and eth_rx.clk.
...
This makes it Xilinx specific, but without it ISE simplifies this as a single signal
(which is fine) but is not able to keep track of the "keep" attribute of both signals
and fails applying the constraints.
2020-03-25 12:40:02 +01:00
8accd6740a
Merge pull request #36 from antmicro/hybrid-mac
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mac: add crossbar for sharing PHY between HW ethernet cores and Wishbone
2020-03-19 22:09:57 +01:00
400ca97f45
examples: increase clk_freq to 125MHz on udp_s7phyrgmii.yml.
2020-03-19 22:01:33 +01:00
ea24ff6993
liteeth_gen: improve readability and add clk_freq checks.
2020-03-19 19:58:35 +01:00
693a6b1513
Merge pull request #35 from Xiretza/standalone-customization
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Allow changing all SoC options through YAML config
2020-03-17 21:45:45 +01:00
2e9121d330
Allow changing all SoC options through YAML config
2020-03-17 18:52:44 +01:00
ac9f6d9f05
mac: add crossbar for sharing PHY between HW ethernet cores and Wishbone
2020-03-13 15:30:36 +01:00
32d4af1148
phy/__init__: import all phys.
2020-03-01 20:13:23 +01:00
b2e12724cc
phy: add tx/rx_clk_freq to phys (useful to add an add_ethernet method in LiteX and simplify timing constraints).
2020-03-01 19:10:39 +01:00
466223e18d
liteeth/gen: update copyrights
2020-02-12 16:50:35 +01:00
d6b58886d2
Merge pull request #34 from Xiretza/generator-improvements
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Generator configuration improvements
2020-02-12 16:44:19 +01:00
7a44209f77
Make memory/CSR regions customizable in config
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Also remove interrupt mapping, since it's unused without a CPU anyway.
2020-02-12 15:55:04 +01:00
ca9cbd1555
Move more options to config file
2020-02-12 15:55:04 +01:00
eea1086654
Use builder arguments in generator
2020-02-12 15:51:53 +01:00
b9fb1f03ec
Remove leftover classes in generator
2020-02-12 15:51:53 +01:00
358bc23cd4
examples/.ymls: add separators
2020-02-12 11:23:33 +01:00
ddcbc33e63
test/test_gen: update
2020-02-12 11:17:38 +01:00
fcadd60cea
liteeth/gen: initial switch to YAML config file (similar to LiteDRAM/LitePCIe)
2020-02-12 00:18:22 +01:00
b0290883d4
Merge branch 'ximinity-generator-lattice'
2020-02-11 23:35:16 +01:00
0954fa32b1
Merge branch 'generator-lattice' of git://github.com/ximinity/liteeth into ximinity-generator-lattice
2020-02-11 23:34:52 +01:00
fcf7b245cb
Merge pull request #33 from Xiretza/standalone-features
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Standalone generator improvements and fixes
2020-02-11 23:14:10 +01:00
5767dfcb6c
Honour --output-dir argument in generator
2020-02-11 22:03:12 +01:00
153c160670
Prioritise overridden interrupts and memory regions
2020-02-11 21:58:41 +01:00
ec9bc578f2
Fix MII tx_en signal width in standalone generator
2020-02-11 21:57:47 +01:00
42a7b6c69d
Allow little-endian interface for standalone design
2020-02-11 21:57:47 +01:00
a696ccddb4
Expose interrupt pin for standalone design
2020-02-11 21:57:02 +01:00
208bc095d9
liteeth/gen: update
2020-02-11 21:45:46 +01:00
ddd0431373
examples: use integrated sram instead of external one. (Also fix regression with new SoC that no longer support address decoders passed to add_wb_slave)
2020-02-11 21:22:13 +01:00
ae10eea860
gen: add lattice support
2020-02-08 16:33:03 +01:00
081bf46ca6
mac/sram: simplify code and improve SRAM read speed using async_read on Memory.
2020-02-07 11:40:14 +01:00
bf4a11ab30
mac/sram: simplify counter (use NextValue in FSM)
2020-02-07 10:57:25 +01:00
721238b7a8
mac/sram: cosmetic changes
2020-02-07 10:53:05 +01:00
f532a12b40
phy/common: use CSRField for MDIO registers
2020-01-28 10:43:33 +01:00
8edf4f3f9a
phy/1000basex: cleanup primitive instances, use Open signal class on open ports, polish code comments
2020-01-28 10:43:08 +01:00
de40a66873
phy/gmii: cleanup BUFGMUX instance
2020-01-28 10:41:53 +01:00
983017a9ed
phy/rgmii: cleanup primitive instances
2020-01-28 10:41:32 +01:00
8a4f38339a
Merge pull request #28 from jersey99/phy-usrgmii
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Changes to get usrgmii and s7rgmii working in hardware
2020-01-28 08:54:09 +01:00
8ecaaf0546
phy/{s7,us}rgmii.py:
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Recent modification that adds S7PLL that in return adds an AsyncResetSynchronizer inside XilinxClocking.
This actually creates a multi-driven net because there is another AsyncResetSync* being added in the Phys.
This change instantiates the PLL without a reset for now, leaving the CD reset intact.
2020-01-27 12:52:10 -08:00
cd413c5c20
phy/usrgmii.py:
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IDELAYE3 requires EN_VTC to be enabled for fixed mode time delay. This eliminates implementation time CRITICAL WARNINGs and ensures generating a bitfile.
2020-01-27 10:32:38 -08:00
3a54bf2b8b
phy/rgmiis: uniformize a bit more
2020-01-18 00:24:40 +01:00
e41f06bbf2
phy: cleanup imports/dw
2020-01-17 23:19:56 +01:00
a48c78044e
phy/s7rgmii/usrgmii: use S7PLL and USPLL
2020-01-17 23:08:38 +01:00
1dab80dd30
Merge pull request #26 from jersey99/marblemini
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A few minor changes that help RGMII phy related debugging. {s6, s7, u…
2020-01-17 22:46:09 +01:00
c16e6b2d86
phy/ecp5rgmii.py: Missed moving dw as class variable here
2020-01-17 12:45:37 -08:00
0a922bb2ad
A few minor changes that help RGMII phy related debugging. {s6, s7, us}rgmii.py Make dw a class variable instead
2020-01-17 09:23:03 -08:00
Florent Kermarrec
Xiretza
Piotr Binkowski
Stefan Schrijvers
Vamsi K Vytla