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1,756 Commits 9 Branches 14 Tags 12 MiB
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1034 Commits

Author SHA1 Message Date
Antoni Pokusinski 01abbc0d50 Replace deprecated register_mem with add_slave 2023-02-15 12:37:33 +01:00
Antoni Pokusinski 934e031dca Fix imports 2023-02-15 12:37:33 +01:00
Tomasz Michalak 223a69cf91 Add platform and target files for Antmicro's sdi mipi video converter board 
Signed-off-by: Tomasz Michalak <tmichalak@antmicro.com>
 2023-02-15 12:37:33 +01:00
Florent Kermarrec fdffeb8474 radiona_ulx4m_ld_v2: Do a first review/cleanup path. 2023-02-13 16:11:32 +01:00
Goran Mahovlic 8c9ea15d0a
Update radiona_ulx4m_ld_v2.py 2023-02-13 12:08:38 +01:00
Goran Mahovlic 404fefaab1
changing filename to radiona 2023-02-13 12:06:04 +01:00
Goran Mahovlic f7822b7dc7
Adding target to files 2023-02-13 11:40:43 +01:00
Florent Kermarrec b8abdf1b39 targets/digilent_arty: Add arguments for XDAC and DNA. 
Avoid specific checks for Vivado toolchain (Now handled by user for f4pga toolchain)
and fix linux-on-litex-vexriscv build.
 2023-01-23 08:55:10 +01:00
Florent Kermarrec b9874685a5 gadgetfactory_papilio_pro: Cosmetic cleanups. 2023-01-17 15:43:12 +01:00
enjoy-digital ec4d203eb6
Merge pull request #471 from Acathla-fr/papilio 
Target/Platform Papilio Pro added (with Arcade MegaWing)
 2023-01-17 11:21:27 +01:00
enjoy-digital 801008f5ad
Merge pull request #469 from hansfbaier/hpcstore-rename 
HPC FPGA Store on AliExpress renamed itself to SITLINV
 2023-01-17 11:20:19 +01:00
Fabien 05ef1ee09e Target/Platform Papilio Pro added (with Arcade MegaWing) 2023-01-16 13:41:24 +01:00
Hans Baier c0773ed9b9 HPC FPGA Store on AliExpress renamed itself to SITLINV 2023-01-16 11:31:35 +07:00
Florent Kermarrec 36a4100c8b ocp_timecard: Add DDR3 SDRAM support. 2023-01-13 12:41:34 +01:00
Florent Kermarrec 3ca298ba42 ocp_tap_timecard: Add TODO on SMAs. 2023-01-13 11:51:09 +01:00
Florent Kermarrec c753bf7fc1 ocp_tap_timecard: Fix GTPE2 location. 2023-01-13 11:47:52 +01:00
Florent Kermarrec 8b0d4787c7 ocp_tap_timecard: Fix CI. 2023-01-13 10:55:07 +01:00
Florent Kermarrec 1e35d78512 ocp_tap_timecard: Add initial SMAIOs peripherals to allow using SMA over PCIe DMA or also with direct (and slow) control/visualization with CSR registers. 2023-01-13 10:08:44 +01:00
Florent Kermarrec a0fd3e7536 Add initial OCP-TAP TimeCard support with PCIe/SPIFlash/Leds/Buttons/DNA/XADC (Compiles but untested). 2023-01-12 18:50:23 +01:00
Luc Lagarde 7a911b8ff6
Allow building digilent_arty using f4pga 
Only use XADC() and DNA() functions if vivado is the current toolchain.
 2023-01-06 16:09:56 -06:00
gatecat 764f64ff1e nx_vip: Add missing 'origin' to SRAM SocRegions 
Signed-off-by: gatecat <gatecat@ds0.me>
 2023-01-04 12:02:11 +01:00
Florent Kermarrec f5643e7c78 machdyne: Fix LiteDRAM PHYs imports (QuarterRateGENSDRPHY not already working?/integrated). 2023-01-01 21:35:51 +01:00
enjoy-digital 563ccbd8cf
Merge pull request #464 from machdyne/master 
initial support for machdyne konfekt and noir
 2023-01-01 16:12:51 +01:00
inc fec82c59e2 remove konfekt ethernet option 2022-12-30 17:36:52 +01:00
inc f0dc9a6874 initial support for machdyne konfekt and noir 2022-12-30 17:00:35 +01:00
stone3311 6cfb56bb07 terasic_deca: add SPI SD card support 2022-12-28 02:13:06 +01:00
Gwenhael Goavec-Merou 4e06e5ff9c targets/xilinx_zybo_z7: adding missing variant parameter to the platform 2022-12-14 07:47:09 +01:00
JoyBed d28894a4b3
Reintroduce original Zybo + HDMI addition (#461) 
* Reintroduce original Zybo support

* Reintroduce original zybo, add HDMI + fixes for Z7
 2022-12-12 22:05:47 +01:00
Florent Kermarrec 12db52471d targets/jungle_electronics_fireant: Update SPIFlash (Make it similar to other boards with BIOS in SPIFlash). 2022-12-08 08:37:13 +01:00
enjoy-digital c05ce32c8a
Merge pull request #458 from trabucayre/arty_s7_tcl_config 
Arty z7 tcl config
 2022-12-08 08:31:22 +01:00
Tim Callahan 6e205be83b Add LedChaser to iCEBreaker-bitsy. 
Signed-off-by: Tim Callahan <tcal@google.com>
 2022-12-04 17:58:20 -08:00
Gwenhael Goavec-Merou a889321535 targets/digilent_arty_z7: adding note to load gateware and bios 2022-12-03 16:54:52 +01:00
Gwenhael Goavec-Merou e71e3ab3ec platforms,targets/digilent_arty_z7: use a dict for PS config instead of fetching file configuration 2022-12-03 16:54:39 +01:00
Gwenhael Goavec-Merou b030630237
Merge pull request #453 from cklarhorst/zybo 
Zybo: Fix for Zynq7000 and use ps7 as submodule for Soft-CPUs
 2022-11-25 21:48:43 +01:00
mkuhn99 53b6bf035a fixed parser 2022-11-24 16:03:12 +01:00
mkuhn99 926ed21f0b fixed review remarks; added zynq7000 as a submodule for using the ps as a slave 2022-11-23 17:20:25 +01:00
mkuhn99 c489347a51 fixed zynq7000 integration; introduced option to add the processing-system as slave to the SoC 2022-11-18 11:19:57 +01:00
Icenowy Zheng 892bf3546d isx_im1283: connect CRG reset to PLL 
This fixes soft reset.

Signed-off-by: Icenowy Zheng <uwu@icenowy.me>
 2022-11-16 15:12:18 +08:00
Icenowy Zheng e27d8c958e isx_im1283: add jtagbone support 
Add necessary script snippets for enabling jtagbone in the command line.

Signed-off-by: Icenowy Zheng <uwu@icenowy.me>
 2022-11-15 21:07:10 +08:00
Florent Kermarrec ae47172d2a targets/decklink_mini_4k: Update clock constraints. 2022-11-14 10:21:42 +01:00
Icenowy Zheng e9d7013d70 sitlinv_stlv7325: add jtagbone support 
Add necessary script snippets for enabling jtagbone in the command line.

Signed-off-by: Icenowy Zheng <uwu@icenowy.me>
 2022-11-13 17:28:04 +08:00
Icenowy Zheng c2c59f5e8c sitlinv_stlv7325: allow to set local/remote ip 
Port the script snippet from Colorlight i5 for setting the local/remote
IP address to STLV7325.

Signed-off-by: Icenowy Zheng <uwu@icenowy.me>
 2022-11-13 17:27:58 +08:00
Icenowy Zheng 27c3afb8fb sitlinv_stlv7325: allow dynamic Ethernet IP 
Currently the sitlinv_stlv7325 target script parses the option that
selects dynamic Ethernet IP; however it's not really passed to LiteETH.

Really pass this option and add an assert that does not allow dynamic
Etherbone IP like other boards.

Signed-off-by: Icenowy Zheng <uwu@icenowy.me>
 2022-11-13 17:27:23 +08:00
Icenowy Zheng 1c07fa94ca sitlinv_stlv7325: fix ident string vendor name 
As we changed the vendor name to proper Sitlinv in the file name, the
ident string is left untouched.

Fix this too.

Signed-off-by: Icenowy Zheng <uwu@icenowy.me>
 2022-11-13 17:27:23 +08:00
Florent Kermarrec 58489ebebf targets/BaseSoC: Cleanup parameters. 2022-11-08 12:31:49 +01:00
Florent Kermarrec a8c92cd86f targets/simple: Switch back to old version for now. 2022-11-08 11:55:06 +01:00
Florent Kermarrec 9e7079c4c8 targets: Remove int() on BaseSoC's sys_clk_freq. 2022-11-08 11:54:17 +01:00
Florent Kermarrec b0e6414519 targets: Cleanup arguments and switch --sys-clk-freq to float (avoid conversion in code). 2022-11-08 10:41:35 +01:00
Florent Kermarrec 16b9677acd targets: Switch to soc_core_argdict. 
The next move was to remove soc_core and only keep soc; so this is probably the right time to do
it in targets to avoid having to handle it later.
 2022-11-07 08:43:26 +01:00
Florent Kermarrec f1e24046fd xilinx_alveo_u250: Fix. 2022-11-06 22:17:28 +01:00