9faa805ab9
alinx_ax7010: Review/Cleanup.
2022-03-17 11:31:02 +01:00
3aa1042f5f
Merge pull request #367 from ggangliu/zynq_xc7z010
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Add ALINX AX7010 board support
2022-03-17 09:52:04 +01:00
496b2cfab9
targets/gowin: Switch to get_bitstream_filename.
2022-03-17 09:40:10 +01:00
773444a7dd
targets: Switch to get_bios_filename/get_bitstream_filename.
2022-03-17 09:21:05 +01:00
94786cae19
Update and rename xilinx_alinx_ax7010.py to alinx_ax7010.py
2022-03-17 11:24:24 +08:00
0745162a29
xilinx_zcu102: Review/Cleanup for consistency with others boards.
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Also remove INTERNAL_VREF constraints that are not yet useful (required for DRAM).
2022-03-16 18:47:05 +01:00
adbcc2e547
add zcu102 target file
2022-03-16 15:55:37 +01:00
9dad1cb244
Rename xilinx_zynq_xc7z010.py to xilinx_alinx_ax7010.py
2022-03-15 15:51:13 +08:00
9c55773275
Add files via upload
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Add zynq_xc7z010 board support
2022-03-12 12:33:41 +08:00
9f9afeaafa
targets/nexys-video: Add support for sata pll refclk
2022-03-11 14:40:21 -05:00
3b74673a93
Merge pull request #363 from curliph/master
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add Gowin programmer support
2022-03-08 17:26:50 +01:00
f52a915487
lambdaconcept_ecpix5: Add initial Video support at 640x480 (with Terminal/Framebuffer).
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I2C intialization code adapted from https://github.com/ultraembedded/ecpix-5 .
Tested with:
- python3 -m litex_boards.targets.lambdaconcept_ecpix5 --cpu-type=firev --with-video-terminal --build --load
- python3 -m litex_boards.targets.lambdaconcept_ecpix5 --cpu-type=firev --with-video-framebuffer --build --load
__ _ __ _ __
/ / (_) /____ | |/_/
/ /__/ / __/ -_)> <
/____/_/\__/\__/_/|_|
Build your hardware, easily!
(c) Copyright 2012-2022 Enjoy-Digital
(c) Copyright 2007-2015 M-Labs
BIOS built on Mar 8 2022 15:34:22
BIOS CRC passed (c7fe9ecd)
Migen git sha1: ac70301
LiteX git sha1: 7ebc7625
--=============== SoC ==================--
CPU: FireV-STANDARD @ 75MHz
BUS: WISHBONE 32-bit @ 4GiB
CSR: 32-bit data
ROM: 128KiB
SRAM: 8KiB
L2: 8KiB
SDRAM: 524288KiB 16-bit @ 300MT/s (CL-6 CWL-5)
--========== Initialization ============--
Initializing SDRAM @0x40000000...
Switching SDRAM to software control.
Read leveling:
m0, b00: |01110000| delays: 02+-01
m0, b01: |00000000| delays: -
m0, b02: |00000000| delays: -
m0, b03: |00000000| delays: -
best: m0, b00 delays: 02+-01
m1, b00: |01110000| delays: 02+-01
m1, b01: |00000000| delays: -
m1, b02: |00000000| delays: -
m1, b03: |00000000| delays: -
best: m1, b00 delays: 02+-01
Switching SDRAM to hardware control.
Memtest at 0x40000000 (2.0MiB)...
Write: 0x40000000-0x40200000 2.0MiB
Read: 0x40000000-0x40200000 2.0MiB
Memtest OK
Memspeed at 0x40000000 (Sequential, 2.0MiB)...
Write speed: 13.6MiB/s
Read speed: 23.4MiB/s
--============== Boot ==================--
Booting from serial...
Press Q or ESC to abort boot completely.
sL5DdSMmkekro
Timeout
No boot medium found
--============= Console ================--
litex> ident
Ident: LiteX SoC on ECPIX-5 2022-03-08 15:34:19
2022-03-08 15:40:52 +01:00
39e4e211bb
targets/decklink_mini_4k: Add build/use instructions.
2022-03-08 14:14:18 +01:00
2df7fd573c
Update sipeed_tang_nano_9k.py
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Add Gowin programmer support
2022-03-08 14:04:28 +08:00
4c9bc53a3c
add Win/powershell and WSL support
2022-03-08 13:24:56 +08:00
ec28ca8fa3
adi_adrv2crr: Add support for the ADI ADRV2CRR with ADRV9009-ZU11EG SoM
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This is a carrier board with a SoM mounted on it.
There is also an FMC connector that can accept another
AD-FMCOMMS8-EBZ to get two more ADRV9009 RFIC but support for
that is not added yet.
Note that the PCIe support requires :
- Change the .xci in the litepcie to use the right Quad
- Revert litex 3c34039b731b42e27e2ee6c8e399e5eb8f3a058f so the
timing constrainst of litepcie apply correctly
Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
2022-03-03 22:17:09 +01:00
0f2e13fdf7
sqrl_fk33: Add HBM2 support (from https://github.com/enjoy-digital/fk33_hbm2_test ).
2022-03-03 17:34:48 +01:00
99a66274c8
xilinx_alveo_u280: Switch HBM2 to USPHBM2 now integrated in LiteX.
2022-03-03 16:11:48 +01:00
b80c7a7843
targets/sqrl_acorn: write_latency_calibration now disabled by default, no longer required.
2022-03-03 15:50:53 +01:00
db2d83ea29
antmicro_datacenter: use 100 MHz and add i2c master
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Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
2022-03-01 13:00:36 +01:00
0b80890119
antmicro_datacenter: add 1 cycle of latency for RCD IC
2022-03-01 12:43:08 +01:00
9976b47f72
antmicro_datacenter: generate outputs for rowhammer-tester
2022-03-01 12:43:08 +01:00
5359fc5bfc
antmicro_datacenter: use A7DDRPHY
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Signed-off-by: Karol Gugala <kgugala@antmicro.com>
2022-03-01 12:43:08 +01:00
2c4d31066f
digilent_arty_z7: Defaults to no_uart.
2022-03-01 11:15:30 +01:00
673676e3cb
digilent_arty_a7: Switch to VivadoProgrammer.
2022-03-01 10:48:22 +01:00
1320f3bd23
Merge pull request #357 from DaveBerkeley/colorlight_i9
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Add ColorLight i9 v7.2
2022-03-01 10:07:55 +01:00
a19c03fa55
targets: Switch to generic/portable HyperRAM core from LiteX.
2022-03-01 09:10:19 +01:00
c9d009c735
Add ColorLight i9 v7.2
2022-02-28 14:08:49 +00:00
1623ba5942
targets/stlv7325: Reduce sys_clk_freq to 100MHz.
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See https://github.com/enjoy-digital/litedram/issues/285 .
2022-02-25 09:04:07 +01:00
872113e1cc
stlv7325: Add SDCard support.
2022-02-24 18:02:43 +01:00
a08f346d90
stlv7325: Add Etherbone support (untested).
2022-02-24 17:43:53 +01:00
b1550f006a
stlv3225: Minor Review/Cleanup, switch to JTAG HS2 programmer.
2022-02-24 17:17:08 +01:00
174d958ca7
Initial support for STLV7325 Kintex-7 board.
2022-02-23 18:28:55 +01:00
6661947d96
Merge pull request #354 from madscientist159/master
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Add initial support for RCS Arctic Tern boards
2022-02-23 18:06:08 +01:00
1717af68ac
targets/sqrl_acorn/ddr3: Disable write_latency_calibration.
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Introduce some memtest failures on some boards.
2022-02-23 10:38:43 +01:00
ae4b3c0938
Add initial support for RCS Arctic Tern boards
2022-02-21 20:04:51 -06:00
85397818d9
add Xilinx ZCU216 support
2022-02-21 19:14:13 +01:00
7d84e6e863
efinix_titanium_ti60_t225: Add SPI/Native SDCard support.
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Both modes working with 8559b88ad8
2022-02-21 10:35:06 +01:00
df36cdbcc9
siglent_sds1104xe: Switch back to native DRAM width (now possible with Nax).
2022-02-18 11:47:08 +01:00
d85f88f42a
siglent_sds1104xe: Reduce DRAM's width to 16-bit for now (to use NaxRiscv).
2022-02-16 17:59:40 +01:00
08a79fa3ac
lattice_ecp5_vip: Minor cleanups, fix CI.
2022-02-15 10:58:38 +01:00
30afe26669
Merge pull request #348 from hubmartin/ecp5-vip
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Draft: Add Lattice ECP5 VIP board + HDMI output board support
2022-02-15 08:53:57 +01:00
896884dd21
Merge branch 'master' into axu2cga_software
2022-02-15 08:21:29 +01:00
3f58df9974
platforms/targets: Fix typos.
2022-02-14 17:26:46 +01:00
5eca41ac73
targets/alinx_axu2cga: adding PS software support (inspired by xilinx_kv260)
2022-02-12 18:24:01 +01:00
d672d9a9b1
targets: s/alinx_axu2gca/alinx_axu2cga/gc
2022-02-12 18:12:45 +01:00
c2cd4410df
Code cleanup, add copyright
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Signed-off-by: hubmartin <hub.martin@gmail.com>
2022-02-12 17:50:07 +01:00
c0e671919d
sqrl_acorn: Downgrade to SATA Gen1 for now (allow lower sys_clk_freq and enough for current tests).
2022-02-09 19:10:12 +01:00
d9b77c6f25
digilent_arty: Add --flash support.
2022-02-09 17:51:56 +01:00
4894926c40
xilinx_kv260: +x.
2022-02-09 16:01:51 +01:00
27b03df886
Add Lattice ECP5 VIP board + HDMI output board support
2022-02-08 21:47:58 +01:00
450a26f395
Merge branch 'master' of https://github.com/litex-hub/litex-boards
2022-02-08 12:55:09 -05:00
7ed633dc4b
add guideline for serial interface
2022-02-08 12:54:34 -05:00
5a0f69502b
enable use of HBM for linux boot
2022-02-08 12:18:38 -05:00
18e8bec9d4
xilinx/kv260: Minor cleanup and add Build/Use instructions (from PR).
2022-02-07 08:12:43 +01:00
8621700916
Merge pull request #345 from sergachev/feature/xilinx_kv260
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Add Xilinx KV260 support
2022-02-07 07:53:55 +01:00
1d8c3789af
add Xilinx KV260 support
2022-02-06 14:38:57 +01:00
617fa26acd
Add 85F to help for orangecrab device
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The 85F orangecrab board exists, and works fine when this option is set to 85F, but leaving it out of the help is a bit confusing.
2022-02-06 10:36:58 +00:00
346623fd06
trellisboard: Rename Video I2C to videoi2c.
2022-02-04 09:26:31 +01:00
6d4fe82179
trellisboard: Rename hdmi_i2c to i2c (to have access to i2c_scan in the BIOS).
2022-02-02 11:08:21 +01:00
0522d8b0c5
trellisboard: Update i2c.add_init call.
2022-02-02 10:59:54 +01:00
7f4d464f1b
trellisboard: Add Video Terminal/Framebuffer support and use new I2C init feature to automatically configure TP410 at startup.
2022-02-02 09:52:12 +01:00
4251cfa865
terasic_de0nano: Add Build/Use instructions with JTAG-UART.
2022-02-01 15:58:34 +01:00
4d45611935
targets: Replace JTAG Atlantic (Deprecated) with JTAG-UART.
2022-02-01 11:30:26 +01:00
9144cb44fb
Merge branch 'master' into jev/deca-eth
2022-01-31 16:22:58 +01:00
fbd424fc48
DECA: Add Ethernet and Etherbone support
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Also fixed pcf_en IO standard compared to golden Arrow project.
2022-01-29 15:15:53 -08:00
9e5224ca49
Add JTAGbone support to Terasic DECA
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Along the way I added UARTbone support to DECA as well for debugging.
Examples:
./terasic_deca.py --csr-csv csr.csv --with-jtagbone --build --load
litex_server --jtag --jtag-config ../prog/openocd_max10_blaster2.cfg
litex_term crossover
./terasic_deca.py --csr-csv csr.csv --uart-name jtag_uart --build --load
litex_term --jtag-config ../prog/openocd_max10_blaster2.cfg jtag
2022-01-27 14:13:58 -08:00
dd134a4b7d
digilent arty z7: allows toolchain selection (PL only)
2022-01-26 07:30:06 +01:00
74395ca80b
digilent_nexyx_video: Add default toolchain value to CRG (to avoid breaking existing designs).
2022-01-25 16:13:57 +01:00
624572f2e9
alinx_axu2gca: Review and do minor cosmetic changes.
2022-01-25 14:58:47 +01:00
537f04a13d
alinx_axu2gca: new board
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Signed-off-by: Gwenhael Goavec-Merou <gwenhael.goavec-merou@trabucayre.com>
2022-01-25 07:35:42 +01:00
621d45cd9e
digilent_arty: Review and improve CRG to avoid specific yosys+nextpnr code.
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sys4x/sys4x_dqs/idelay clks can be disabled when integrated-main-ram is used.
2022-01-24 19:16:07 +01:00
c2276c1e6d
Merge pull request #338 from suarezvictor/master
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Add tweaks to Arty board to support yosys+nextpnr toolchain
2022-01-24 19:02:59 +01:00
1abb03e514
tang_nano_4k: Review/Cleanup:
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- Revert abstractions on clk_name/period: Too much abstraction to avoid duplications makes the code more difficult to read.
ex:
- When constraining clk27, frequency is already in the name.
- In the target, we want to know we are using clk27 as the main clk.
- We need a default sys_clk_freq for project only importing BaseSoC.
- Revert SPI Flash import (for consistency with other targets).
- Keep VexRiscv as default CPU since this target is able to run it and also for consistency with other targets.
2022-01-24 18:46:51 +01:00
e357eb6d8f
Merge pull request #337 from sergachev/tang_nano_4k_emcu
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Enable LiteX BIOS on ARM core on Tang nano 4K
2022-01-24 18:36:10 +01:00
cc1b46f106
tang_nano_9k: Fix HyperRAM integration.
2022-01-24 18:35:12 +01:00
db77ea5c7a
Add tweaks to Arty board to support yosys+nextpnr toolchain
2022-01-24 02:06:34 -03:00
6238052b10
tang nano 4k: disable spi flash with gowin emcu, cleanup
2022-01-23 16:10:46 +01:00
6c81fc708c
tang nano 4k: add memory regions, set default cpu
2022-01-23 13:05:51 +01:00
787f44e7d9
Merge pull request #336 from tcal-x/cmod-a7-flash
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Digilent CMOD A7: add flash support.
2022-01-23 08:36:49 +01:00
6567af6f49
Digilent CMOD A7: add flash support.
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Add both "--flash" and "--with-spi-flash"; tested on board.
4MB flash mapped at 0x00400000.
Signed-off-by: Tim Callahan <tcal@google.com>
2022-01-22 18:50:12 -08:00
f533e7f8ba
sipeed_tang_nano_9k: enable copackaged PSRAM
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Also enable SPI SDCard which was pending by the lack of main_ram
previously.
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
2022-01-23 03:37:03 +08:00
999dbd572f
Merge pull request #334 from Icenowy/tang9k
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sipeed_tang_nano_9k: new board
2022-01-22 15:49:08 +01:00
e699c377a5
sipeed_tang_nano_9k: new board
...
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
2022-01-22 11:45:49 +08:00
e9d4d9066a
xilinx_zcu106: add DDR4 interface and fix reset error
2022-01-22 03:08:21 +08:00
b8aad4b030
Merge pull request #332 from tcal-x/prog-cmod-a7
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Add openocd programmer for Digilent CMOD A7.
2022-01-21 08:05:22 +01:00
e0c4c0fe39
Add openocd programmer for Digilent CMOD A7.
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Signed-off-by: Tim Callahan <tcal@google.com>
2022-01-20 20:54:03 -08:00
0e91013fc7
quickfeather: fix path to libeos library when board script called not from its directory; fix wget redownloads; add libeos to gitignore
2022-01-20 18:43:59 +01:00
5f2ccb2d32
targets: Switch from bridge to crossover.
2022-01-19 17:03:17 +01:00
abb54cebb3
trenz_c10lprefkit: Add Etherbone support.
2022-01-19 14:47:14 +01:00
1ce978806d
Merge pull request #328 from sergachev/fix/zedboard_software
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Fix Zedboard software
2022-01-19 10:05:49 +01:00
f11106e9c5
targets/digilent_cmod_a7: Simplify/Cleanup.
2022-01-19 10:03:20 +01:00
f8e3cc5361
Merge pull request #327 from bl0x/digilent_cmod_a7
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digilent_cmod_a7: Remove unused clocks.
2022-01-19 09:59:44 +01:00
bbf13f4439
zedboard: remove a hack
2022-01-19 02:41:11 +01:00
4f4d47dcdd
zedboard: correct memory map
2022-01-19 02:40:54 +01:00
fccb952c4b
target: Remove ident_version=True no longer required.
2022-01-18 17:13:02 +01:00
7114911cea
targets: --no-ident-version is now directly provided by LiteX, remove it on targets implementing it.
2022-01-18 16:47:38 +01:00
d92a2b82fb
targets/l2_cache_reverse: Now defaulting to False in LiteX, so setting it to False for correct Framebuffer operations is no longer required.
2022-01-18 11:37:55 +01:00
2c26f07a5a
digilent_cmod_a7: Remove unused clocks.
2022-01-17 22:49:10 +01:00
12fa844b56
decklink_mini_4k: Add dedicated SATA PLL to allow SATA + Framebuffer.
2022-01-17 18:11:52 +01:00
Florent Kermarrec
Yonggang Liu
Joseph Faye
Gabriel Somlo
curliph
Sylvain Munaut
Alessandro Comodi
Piotr Binkowski
Karol Gugala
Dave Berkeley
Andrew Gillham
Raptor Engineering Development Team
Ilia Sergachev
Gwenhael Goavec-Merou
hubmartin
Sergiu Mosanu
Ben Stobbs
Jevin Sweval
Victor Suarez Rovere
Tim Callahan
Icenowy Zheng
vacajk
Bastian Löher