Sebastien Bourdeauducq
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264be80f2d
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Fix syntax errors and other stupid problems
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2012-02-13 22:28:02 +01:00 |
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Sebastien Bourdeauducq
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8a61d9d121
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bus/csr: Rename a->adr d->dat to be consistent with the other buses
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2012-02-13 21:46:39 +01:00 |
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Sebastien Bourdeauducq
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060426cb59
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bus/wishbone2asmi: set WM, and send 0 when inactive
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2012-02-13 16:49:43 +01:00 |
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Sebastien Bourdeauducq
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cad9d3b960
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bus: Wishbone to ASMI caching bridge (untested)
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2012-02-13 16:29:38 +01:00 |
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Sebastien Bourdeauducq
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7894411418
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bus/asmibus: fix typo
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2012-02-11 20:56:01 +01:00 |
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Sebastien Bourdeauducq
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ef436a1ec9
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bus/asmibus: add get_slots, fix get_fragment
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2012-02-10 17:49:06 +01:00 |
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Sebastien Bourdeauducq
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945d655d45
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bus: ASMI hub (untested)
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2012-02-10 15:21:04 +01:00 |
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Sebastien Bourdeauducq
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47883675db
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bus/wishbone2csr: truncate WB data
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2012-02-06 18:43:34 +01:00 |
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Sebastien Bourdeauducq
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a99c2acfa8
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Remove explicit bus names and rely on the new automatic namer
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2012-01-27 22:20:57 +01:00 |
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Sebastien Bourdeauducq
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076c171c7b
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Use meaningful class names
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2012-01-20 23:07:32 +01:00 |
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Sebastien Bourdeauducq
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77b3c8e3bb
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bus: list signals
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2012-01-15 15:48:51 +01:00 |
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Sebastien Bourdeauducq
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20425703fa
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Wishbone: omit fixed LSBs
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2012-01-13 17:29:05 +01:00 |
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Sebastien Bourdeauducq
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566295dea3
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csr: use optree
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2011-12-22 19:36:56 +01:00 |
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Sebastien Bourdeauducq
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ba40f58491
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corelogic: operator tree
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2011-12-22 15:46:19 +01:00 |
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Sebastien Bourdeauducq
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107f03fd4b
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Remove uses of declare_signal
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2011-12-18 21:47:48 +01:00 |
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Sebastien Bourdeauducq
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1a845d4553
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32-device, 8-bit CSR bus
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2011-12-17 15:54:49 +01:00 |
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Sebastien Bourdeauducq
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c7b9dfc203
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fhdl: simpler syntax
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2011-12-16 21:30:14 +01:00 |
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Sebastien Bourdeauducq
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39b7190334
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Pay a bit more attention to PEP8
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2011-12-16 16:02:55 +01:00 |
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Sebastien Bourdeauducq
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929cc98070
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wishbone2csr: wait for WB deack
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2011-12-13 17:38:59 +01:00 |
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Sebastien Bourdeauducq
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92f24b784d
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wishbone: decoder: fix slave cyc generation in registered mode
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2011-12-13 14:08:39 +01:00 |
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Sebastien Bourdeauducq
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0ea7a9b2e6
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wishbone2csr: fix double-write bug
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2011-12-13 00:25:46 +01:00 |
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Sebastien Bourdeauducq
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923fc52e68
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wishbone: only send ack to the active master in arbiter
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2011-12-13 00:25:25 +01:00 |
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Sebastien Bourdeauducq
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16a6029a1b
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bus: fix CSR interconnect data readback
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2011-12-11 20:17:12 +01:00 |
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Sebastien Bourdeauducq
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dad9120653
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bus: 14-bit CSR addresses
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2011-12-11 20:16:50 +01:00 |
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Sebastien Bourdeauducq
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05d91c7104
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bus: Wishbone to CSR bridge
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2011-12-11 15:04:34 +01:00 |
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Sebastien Bourdeauducq
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4d1a960308
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wishbone: decoder + shared bus interconnect
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2011-12-09 13:11:52 +01:00 |
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Sebastien Bourdeauducq
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5c7131dc86
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wishbone: arbiter
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2011-12-08 23:21:25 +01:00 |
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Sebastien Bourdeauducq
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c1041b9a5f
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simplebus: export GetSigName function
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2011-12-08 23:06:04 +01:00 |
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Sebastien Bourdeauducq
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7c99e51b90
|
Named buses
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2011-12-08 19:16:08 +01:00 |
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Sebastien Bourdeauducq
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5720a51dad
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wishbone: add missing SEL
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2011-12-08 19:09:32 +01:00 |
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Sebastien Bourdeauducq
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c43f3da534
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Wishbone declarations
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2011-12-08 18:47:41 +01:00 |
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Sebastien Bourdeauducq
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a6b86168ce
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Simple bus base class
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2011-12-08 18:47:32 +01:00 |
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Sebastien Bourdeauducq
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458cfc8623
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CSR bus definitions
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2011-12-05 00:16:44 +01:00 |