a95f1b8486
cores/hyperbus: Make latency dynamically configurable.
2024-04-15 12:06:11 +02:00
6216bd4e99
cores/hyperbus: Add latency_mode parameter and test different latencies/modes in simulation.
2024-04-15 10:32:13 +02:00
33a1fcda48
software/bios: Do minimal reconfiguration for variable latency and start testing latency cycles re-configuration.
2024-04-12 19:35:31 +02:00
f8c59c03e3
cores/hyperbus: Add variable latency support (working on ti60 f225).
2024-04-12 18:50:19 +02:00
b192103822
cores/hyperbus: Fix bytes order on register writes.
2024-04-12 16:06:26 +02:00
fb519ac260
test/test_hyperbus: Add test_hyperram_reg_write.
2024-04-12 15:21:57 +02:00
a32db7abad
cores/hyperbus: Add with_csr parameter to make Register interface optional.
2024-04-12 15:21:32 +02:00
2d1dd45fd2
Merge pull request #1919 from nrndda/uart_tx_irq_handling_fix
...
Uart tx irq handling fix
2024-04-12 10:45:12 +02:00
2bc41928a3
Merge pull request #1916 from motec-research/spi_mmap
...
SPIMMAP bug fixes and new features
2024-04-12 10:38:05 +02:00
a891b2dd11
Merge pull request #1904 from machdyne/master
...
litex_json2dts_linux: Add support for multiple Ethernet interfaces
2024-04-12 10:32:12 +02:00
5d895bd3a7
Merge branch 'master' into master
2024-04-12 10:32:05 +02:00
441d05ee36
core/hyperbus: Start testing Register writes.
2024-04-11 18:39:48 +02:00
59756b4342
cores/hyperbus: Test and fix HyperRAM register read accesses.
...
Seems OK:
Identification Register 0 : 00000e76
Identification Register 1 : 00000009
Configuration Register 0 : 00008f2f
Configuration Register 1 : 0000ffc1
reg_control: 302
reg_status: 2
reg_debug: 8
2024-04-11 18:29:48 +02:00
2384d6fbd4
cores/hyperbus: Add initial HyperRAM Register access over CSRs.
...
Will be used to get HyperRAM characteristics and also to configure latency and enable varialble latency.
Untested yet.
2024-04-11 17:51:47 +02:00
b8ca87ece5
build/openocd: disabled 'poll off' because not supported by ECP5
2024-04-11 15:13:52 +02:00
62cf95c5da
cpu/vexii add git
2024-04-10 12:21:47 +02:00
555f89c22a
set default l2 ways to 4
2024-04-08 17:16:15 +02:00
9654b40864
Got litex dma to work with vexii
2024-04-08 16:45:15 +02:00
8f86108eed
tools/litex_json2dts add vexiiriscv
2024-04-08 14:40:44 +02:00
6885770e47
Uart tx irq handling fix
2024-04-07 17:39:30 +03:00
3864615f6f
tools/litex_json2dts_linux.py: improved cpu_isa_extension attribute (fdc) and fixed kernel panic during rocket booting with linux
2024-04-06 08:13:56 +02:00
06009c57a3
build/xilinx/common: Fix missing clk parameter on XilinxSDRTristateImpl.
2024-04-05 16:04:29 +02:00
5ae098ebc6
test/spi_mmap: be less verbose
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don't print miso/mosi changes with -v
2024-04-05 12:35:47 +11:00
c2da8de7b0
test_spi_mmap: tests for slot 0&1
2024-04-05 12:35:47 +11:00
07cfda119d
interconnect/wishbone: check err in simulation
2024-04-05 12:35:47 +11:00
416f1b4281
cores/spi_mmap: add slot post transfer cs_wait
...
Also remove unused slot_status - maintains CSR alignment now that
slot_control is 64 bit (two 32bit registers).
2024-04-05 12:35:47 +11:00
f3b287addd
cores/spi_mmap: add 24-bit slot length
2024-04-05 12:31:39 +11:00
5d1fa7b6ca
cores/spi_mmap: fix data if bus width > length
...
Details:
* 32bit bus write to 8 and 16bit MSB first slot resulted
in shifted data on mosi.
* 32bit read from 8 and 16bit LSB first slot resulted
with shifted data in fifo.
Fixes 2 tests - all current tests now pass.
2024-04-05 12:31:39 +11:00
422b02cc16
cores/spi_mmap: fix data in unused rx_fifo bits
...
clear miso at start. Prevent previous transfer data in unused bits
with 8 and 16bit slot lengths and 32bit bus read. Fixes 2 tests.
2024-04-05 12:31:39 +11:00
a9c007d8d7
test/spi_mmap: add some SPIMMAP tests
...
Some pass and some fail demonstrating issues observed in driver
development.
run unittest with -v to see more test details.
Ran 9 tests in 4.161s
FAILED (failures=4)
2024-04-05 12:31:39 +11:00
4bc47c959f
test/spi_mmap: lint and autoformat with Ruff
2024-04-05 12:31:39 +11:00
2e67f6a1a3
soc/cores/spi_mmap: add read only slot count register
2024-04-05 12:31:39 +11:00
3477aeaca1
soc/cores/spi_mmap: add read only version register
2024-04-05 12:31:39 +11:00
6170c90459
soc/cores/spi_mmap: adjust CSR mapping to better suit drivers
...
Currently the TX_RX_ENGINE CSR register lives below the
slot registers which are dynamic in length (based on how
many slots (chip selects) are configured in the gateware).
Move the TX_RX_ENGINE CSR to above the SLOT configuration
registers so TX_RX_ENGINE never moves.
This makes for an easier and cleaner driver.
2024-04-05 12:31:39 +11:00
dc78c3f47b
soc/interconnect/stream/ClockDomainCrossing: Add a Buffer when same Clk Domains when buffered=True.
2024-04-04 13:02:17 +02:00
a36fbc86ea
Merge pull request #1911 from davidar/sim-vsync
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sim/video: Add option to render only on frame vsync
2024-04-02 10:54:05 +02:00
7ad444b2a9
Merge pull request #1912 from motec-research/efinity_fix_pin_name
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build/efinix/platform: fix get_pin_name()
2024-04-02 10:48:19 +02:00
38a8a171dd
integration/builder: Replace soc_core's initialize_memory with optional "init_mems" method.
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Make sure to also attach Builder to SoC to allow easily get/use builder properties in init_mems method.
2024-04-02 10:43:01 +02:00
31508ddfa4
soc: Add separators for SoC Main Components.
2024-04-02 10:25:59 +02:00
06083c7863
soc/init_ram: Define and use contents_size.
2024-04-02 10:21:35 +02:00
ca04858b39
integration/builder: Switch to SoC.init_rom directly and remove initialize_rom that is no longer used.
2024-04-02 10:16:43 +02:00
175aab73a8
soc/SoC: Add init_ram method from init_rom, allowing initilization of any RAM of the SoC and switch init_rom to it.
2024-04-02 10:09:38 +02:00
9f49b13f8c
soc_core: Minor cosmetic changes.
2024-04-02 09:15:33 +02:00
f181eabebb
soc/init_rom: Add SoCError when ROM Size < Contents Size and cosmetic cleanups.
2024-04-02 09:12:03 +02:00
0601bf51c4
Merge pull request #1856 from motec-research/soc_initialize_memory
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soc/builder: add initialize_memory()
2024-04-02 17:30:12 +11:00
0cb101da25
build/efinix/platform: fix get_pin_name()
...
get_pin_name did not include the resource index, so additional core
instances were generated with identical pin names. See below for
examples.
Also only adds slice index for slices with more than one io for cleaner
naming.
("i2c", 0,
Subsignal("scl", Pins(...)),
Subsignal("sda", Pins(...)),
),
("i2c", 1,
Subsignal("scl", Pins(...)),
Subsignal("sda", Pins(...)),
),
Before:
output wire i2c0_oe,
input wire i2c0_scl,
input wire i2c0_sda,
input wire i2c1_scl,
input wire i2c1_sda,
input wire i2c_scl0_IN,
input wire i2c_scl0_IN_1,
input wire i2c_scl0_IN_2,
output wire i2c_scl0_OE,
output wire i2c_scl0_OE_1,
output wire i2c_scl0_OE_2,
input wire i2c_sda0_IN,
input wire i2c_sda0_IN_1,
input wire i2c_sda0_IN_2,
output wire i2c_sda0_OE,
output wire i2c_sda0_OE_1,
output wire i2c_sda0_OE_2,
After:
output wire i2c0_oe,
input wire i2c0_scl,
input wire i2c0_scl_IN,
output wire i2c0_scl_OE,
output wire i2c0_scl_OUT,
input wire i2c0_sda,
input wire i2c0_sda_IN,
output wire i2c0_sda_OE,
output wire i2c0_sda_OUT,
input wire i2c1_scl,
input wire i2c1_scl_IN,
output wire i2c1_scl_OE,
output wire i2c1_scl_OUT,
input wire i2c1_sda,
input wire i2c1_sda_IN,
output wire i2c1_sda_OE,
output wire i2c1_sda_OUT,
2024-04-02 11:52:31 +11:00
a763e82d86
soc/builder: add initialize_memory()
...
Allows the target soc to override memory initialization:
rom and/or ram.
2024-04-02 11:37:31 +11:00
5d2676482f
sim/video: Add option to render only on frame vsync
2024-03-29 11:24:16 +10:00
87137c3027
CHANGES.md: Update.
2024-03-28 14:24:12 +01:00
7b0985a6bc
Merge pull request #1909 from davidar/sim-rgba
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sim/video: Change pixel format to RGBA
2024-03-28 14:21:24 +01:00
Florent Kermarrec
Gwenhael Goavec-Merou
Dolu1990
Dmitry Derevyanko
Andrew Dennison
Richard Tucker
AndrewD
David A Roberts