Florent Kermarrec
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1620f9c5b0
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soc/CSR: show alignment in report and add info when updating.
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2020-02-12 21:55:30 +01:00 |
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Florent Kermarrec
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5b34f4cd34
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soc/add_cpu: use cpu.data_width as CSR alignment, fix regression on Rocket
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2020-02-12 21:25:52 +01:00 |
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Florent Kermarrec
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2f69f607e3
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integration/soc: fix refactoring issues
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2020-02-12 18:16:38 +01:00 |
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Florent Kermarrec
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1d6ce66bf7
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soc/integration/builder: update copyright, align arguments
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2020-02-12 16:43:11 +01:00 |
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enjoy-digital
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98ae91ada5
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Merge pull request #383 from Xiretza/builder-directories
Unify output directory handling in builder
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2020-02-12 16:38:04 +01:00 |
Xiretza
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b56545791c
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Unify output directory handling in builder
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2020-02-12 15:47:16 +01:00 |
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enjoy-digital
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4a15c3e219
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Merge pull request #382 from enjoy-digital/new_soc
Add new SoC/LiteXSoC classes and use it for SoCCore/SoCSDRAM
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2020-02-11 18:39:33 +01:00 |
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Florent Kermarrec
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e9c665a539
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soc_core/soc_sdram: add disclaimer
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2020-02-11 18:28:05 +01:00 |
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Florent Kermarrec
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5558865cbf
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soc_core: provide full retro-compatibily when add_wb_slave is called before add_memory_region
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2020-02-11 18:21:41 +01:00 |
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Florent Kermarrec
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1b5caf56fb
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soc: fix busword typo
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2020-02-11 17:57:05 +01:00 |
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Florent Kermarrec
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8b5cc34553
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targets/EthernetSoC: be sure memory region is added before adding Wishbone Slave (required by new SoC)
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2020-02-11 17:44:24 +01:00 |
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enjoy-digital
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240a55bace
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Merge branch 'master' into new_soc
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2020-02-11 17:22:06 +01:00 |
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Florent Kermarrec
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d5ad1d56f2
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soc/integration: move mem_decoder to soc_core
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2020-02-11 17:19:22 +01:00 |
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Florent Kermarrec
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0a737cb624
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soc/integration/common: simplify get_version
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2020-02-11 17:16:24 +01:00 |
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Florent Kermarrec
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399b65fa17
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soc/add_uart: fix bridge
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2020-02-11 16:55:37 +01:00 |
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Florent Kermarrec
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160c55d1d4
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soc_core/soc_sdram: remove disclaimer (we'll add it later when designs will be adapted)
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2020-02-11 16:44:25 +01:00 |
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Florent Kermarrec
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b2c66b1efd
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soc: avoid double definition of main_ram
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2020-02-11 16:39:37 +01:00 |
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Florent Kermarrec
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5f9946085b
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soc: improve log colors on error reporting
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2020-02-11 16:24:57 +01:00 |
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Florent Kermarrec
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b22d2ca02b
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soc: add linker regions management
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2020-02-11 15:28:02 +01:00 |
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Florent Kermarrec
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abc31a92c6
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soc: improve log presentation/colors
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2020-02-11 14:50:16 +01:00 |
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Florent Kermarrec
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91e2797bb4
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soc: fix cpu_reset_address
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2020-02-11 14:17:32 +01:00 |
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Florent Kermarrec
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0d7430fc69
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tools/litex_sim_new: remove
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2020-02-11 14:05:01 +01:00 |
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Florent Kermarrec
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21d38701df
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soc: fix build_time format
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2020-02-11 13:23:53 +01:00 |
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Florent Kermarrec
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4d761e1afd
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cores/cpu: remove separators on io_regions (requires python 3.6)
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2020-02-11 13:12:54 +01:00 |
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enjoy-digital
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7c57a33ba0
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Merge pull request #380 from Xiretza/cpunone-all-io
Allow all memory regions to be used as IO with CPUNone
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2020-02-11 13:11:33 +01:00 |
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Florent Kermarrec
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b43d830fda
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soc/add_sdram: simplify L2 Cache, use FullMemoryWE on L2 Cache by default (seems better on all devices)
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2020-02-11 09:30:45 +01:00 |
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Florent Kermarrec
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ea8e745ac2
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soc_core/common: move old mem_decoder to soc_core, simplify get_version
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2020-02-11 08:44:23 +01:00 |
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Xiretza
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e301df7f56
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Allow all memory regions to be used as IO with CPUNone
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2020-02-10 19:56:36 +01:00 |
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Florent Kermarrec
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16d1972bf8
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integration/common: fix mem_decoder (shadow base has been deprecated)
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2020-02-10 19:40:56 +01:00 |
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Florent Kermarrec
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5e11e8391f
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tools/litex_sim_new: switch to dynamically allocated ethmac origin
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2020-02-10 19:37:53 +01:00 |
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Florent Kermarrec
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dd0c71d7a1
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soc/SoCRegion/Decoder: pass bus to decoder and remove mask on origin
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2020-02-10 19:34:18 +01:00 |
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Florent Kermarrec
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e8e4537e14
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soc/add_sdram: avoid L2 cache when l2_cache_size == 0.
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2020-02-10 19:02:44 +01:00 |
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Florent Kermarrec
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dcbdb73231
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soc: remove unneeded \n
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2020-02-10 18:38:59 +01:00 |
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Florent Kermarrec
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0f1811fb51
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tools/litex_sim_new: use new bus/csr/irq methods
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2020-02-10 18:21:41 +01:00 |
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Florent Kermarrec
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d320be8ecb
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soc: use io_regions for alloc_region
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2020-02-10 18:19:35 +01:00 |
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Florent Kermarrec
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9ac09ddde5
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tools: add litex_sim_new based on SoCCore and using add_sdram method
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2020-02-10 18:00:46 +01:00 |
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Florent Kermarrec
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cbcd953dd7
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soc_core: use add_rom
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2020-02-10 17:43:29 +01:00 |
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Florent Kermarrec
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487ac3da9a
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soc/add_cpu: simplify CPUNone integration
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2020-02-10 17:40:46 +01:00 |
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Florent Kermarrec
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f7d4648ca1
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soc/SoCBusHandler: add add_adapter method and use it to convert Master/Slave before connecting to the Bus
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2020-02-10 17:17:31 +01:00 |
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Florent Kermarrec
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379d47a843
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soc/add_sdram: add sdram csr
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2020-02-10 17:02:20 +01:00 |
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Florent Kermarrec
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3921b6345c
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soc/add_sdram: fix rocket, shorten comments
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2020-02-10 16:55:15 +01:00 |
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Florent Kermarrec
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14b627b466
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soc/add_sdram: improve API
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2020-02-10 16:38:20 +01:00 |
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Florent Kermarrec
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1faefdc0fa
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soc: add LiteXSoC class and mode add_identifier/uart/sdram to it
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2020-02-10 16:28:11 +01:00 |
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Florent Kermarrec
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11dbe19084
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soc_core/sdram: cleanup, add disclaimer
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2020-02-10 16:21:21 +01:00 |
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Florent Kermarrec
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5eb88cd904
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soc: add add_sdram
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2020-02-10 16:01:19 +01:00 |
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Florent Kermarrec
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39011593ac
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soc: add csr_regions, update copyright
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2020-02-10 15:11:37 +01:00 |
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Florent Kermarrec
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d2b069516a
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soc: add cpu rom/sram check
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2020-02-10 14:48:46 +01:00 |
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Florent Kermarrec
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de100fddf5
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soc: add SOCIORegion and manage it
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2020-02-10 14:36:53 +01:00 |
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Florent Kermarrec
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6b8c425f9b
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soc: reorder main components/peripherals
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2020-02-10 13:07:09 +01:00 |
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Florent Kermarrec
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84b5df7871
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soc: add add_cpu method
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2020-02-09 21:56:32 +01:00 |