Sebastien Bourdeauducq
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51bec340ab
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sim: remove PureSimulable (superseded by Module)
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2013-03-15 19:41:30 +01:00 |
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Sebastien Bourdeauducq
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04df076fba
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bank: automatic register naming
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2013-03-12 15:45:24 +01:00 |
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Sebastien Bourdeauducq
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80970b203c
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bus/asmibus: use implicit finalization
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2013-03-11 17:11:59 +01:00 |
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Sebastien Bourdeauducq
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174e8cb8d6
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bus/asmibus: use fhdl.module API
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2013-03-10 19:28:22 +01:00 |
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Sebastien Bourdeauducq
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2b8dc52c13
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Use common definition for FinalizeError
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2013-03-09 19:03:13 +01:00 |
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Sebastien Bourdeauducq
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b75fb7f97c
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csr/SRAM: support for writes with memory widths larger than bus words
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2013-03-09 00:50:57 +01:00 |
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Sebastien Bourdeauducq
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9b4ca987e0
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bus/csr: support memories with larger word width than the bus (read only)
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2013-03-03 19:27:13 +01:00 |
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Sebastien Bourdeauducq
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d2491828a4
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csr/SRAM: prefix page register with memory name
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2013-03-01 12:06:12 +01:00 |
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Sebastien Bourdeauducq
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f9acee4e68
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corelogic -> genlib
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2013-02-22 23:19:37 +01:00 |
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Sebastien Bourdeauducq
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49cfba50fa
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New 'specials' API
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2013-02-22 17:56:35 +01:00 |
|
Sebastien Bourdeauducq
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3fae6c8f03
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Do not use super()
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2012-12-18 14:54:33 +01:00 |
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Sebastien Bourdeauducq
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280a87ea69
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elsewhere: do not create interface in default param
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2012-12-06 17:34:48 +01:00 |
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Sebastien Bourdeauducq
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c3fdf42825
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bus/csr: add SRAM
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2012-12-06 17:16:17 +01:00 |
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Sebastien Bourdeauducq
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4bcb39699b
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bus/wishbone/sram: accept memories < 32 bits
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2012-12-01 13:04:22 +01:00 |
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Sebastien Bourdeauducq
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523816982a
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bus/wishbone: add SRAM
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2012-12-01 12:59:09 +01:00 |
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Sebastien Bourdeauducq
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d8e478efee
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Replace Signal(bits_for(... with Signal(max=...
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2012-11-29 21:53:36 +01:00 |
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Sebastien Bourdeauducq
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50ed73c937
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New specification for width and signedness
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2012-11-29 21:22:38 +01:00 |
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Sebastien Bourdeauducq
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fee22a4631
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Remove Constant
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2012-11-28 23:18:43 +01:00 |
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Sebastien Bourdeauducq
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5183774ec8
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bus/wishbone2asmi: do not use MemoryPort
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2012-11-26 19:14:59 +01:00 |
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Sebastien Bourdeauducq
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ab31b4d99c
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bus: memory initiator
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2012-11-23 16:22:50 +01:00 |
|
Sebastien Bourdeauducq
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d4baac6c0f
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bus/csr: allow specifying existing interface
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2012-11-17 19:44:25 +01:00 |
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Sebastien Bourdeauducq
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86090e1cbd
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bus/asmibus: swap port position to be consistent with wishbone API
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2012-11-17 19:42:39 +01:00 |
|
Sebastien Bourdeauducq
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ece786d6aa
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bus/wishbone: allow specifying existing interface
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2012-11-17 19:42:06 +01:00 |
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Sebastien Bourdeauducq
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d0d4c48098
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bus/transactions: add busname parameter
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2012-11-17 19:36:08 +01:00 |
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Sebastien Bourdeauducq
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4164fb4ac9
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bus/csr: configurable data width
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2012-08-26 21:19:34 +02:00 |
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Sebastien Bourdeauducq
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8de192dfbd
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x.bv.width -> len(x)
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2012-07-13 18:32:54 +02:00 |
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Sebastien Bourdeauducq
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b4613d913f
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bus/wishbone: remove use of deprecated multimux
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2012-07-13 17:17:20 +02:00 |
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Sebastien Bourdeauducq
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8062e48697
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bus/asmibus: fix per-port tag generation
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2012-07-12 19:37:50 +02:00 |
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Sebastien Bourdeauducq
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c82a468506
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bus: CSR initiator
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2012-07-07 22:36:15 +02:00 |
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Sebastien Bourdeauducq
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8a23451237
|
PureSimulable
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2012-06-12 17:08:56 +02:00 |
|
Sebastien Bourdeauducq
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a591510189
|
ASMI simulation models
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2012-06-12 16:57:00 +02:00 |
|
Sebastien Bourdeauducq
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b7a84b3750
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wishbone: base TargetModel class
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2012-06-10 17:05:10 +02:00 |
|
Sebastien Bourdeauducq
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ec501e7797
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bus/wishbone: target model
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2012-06-10 16:40:33 +02:00 |
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Sebastien Bourdeauducq
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f061b25a24
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bus/wishbone/Tap: remove ack feature
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2012-06-10 12:46:24 +02:00 |
|
Sebastien Bourdeauducq
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11674242c4
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Use super() instead of calling parent constructors directly
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2012-06-08 18:06:12 +02:00 |
|
Sebastien Bourdeauducq
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68cd445662
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bus/wishbone2asmi: fix cache tag size
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2012-05-15 15:18:03 +02:00 |
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Sebastien Bourdeauducq
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0bea1e2589
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asmi: dat_wm high to disable data write
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2012-05-15 14:41:54 +02:00 |
|
Sebastien Bourdeauducq
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f2c20e4af0
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bus/asmibus/hub: hack to prevent comb loops
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2012-04-30 17:11:42 -05:00 |
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Sebastien Bourdeauducq
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6e3b25ebb6
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bus/dfi: reset active low signals to 1
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2012-04-01 17:43:24 +02:00 |
|
Sebastien Bourdeauducq
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94b02aa8ed
|
bus/asmicon: initiator
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2012-03-30 22:16:31 +02:00 |
|
Sebastien Bourdeauducq
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e969b9afc3
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corelogic: convert timeline to function and move to misc
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2012-03-15 20:25:44 +01:00 |
|
Sebastien Bourdeauducq
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1665f293a6
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bus/asmibus/hub: require finalization before get_slots
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2012-03-14 16:19:29 +01:00 |
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Sebastien Bourdeauducq
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5c0cc6292c
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fhdl: export log2_int
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2012-03-14 12:19:42 +01:00 |
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Sebastien Bourdeauducq
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ab800fa2ed
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bus: generic transaction model
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2012-03-08 18:14:06 +01:00 |
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Sebastien Bourdeauducq
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1b8cb5b46c
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bus/dfi: fix multiphase naming
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2012-02-19 17:57:04 +01:00 |
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Sebastien Bourdeauducq
|
92dfbb92dd
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bus: add interconnect statements function
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2012-02-17 23:51:32 +01:00 |
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Sebastien Bourdeauducq
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c08687b9c6
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bus/dfi: filter signals by direction
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2012-02-15 21:48:05 +01:00 |
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Sebastien Bourdeauducq
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fa9cf3e466
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bus: add DFI
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2012-02-15 18:09:14 +01:00 |
|
Sebastien Bourdeauducq
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af5230c8ee
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bus: fix simple interconnect
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2012-02-15 16:42:05 +01:00 |
|
Sebastien Bourdeauducq
|
0493212124
|
bus: simplify and cleanup
Unify slave and master interfaces
Remove signal direction suffixes
Generic simple interconnect
Wishbone point-to-point interconnect
Description filter (get_name)
Misc cleanups
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2012-02-15 16:30:16 +01:00 |