Sebastien Bourdeauducq
|
d2cbc70190
|
bank/description: memprefix
|
2013-02-25 23:14:15 +01:00 |
|
Sebastien Bourdeauducq
|
a81781f589
|
fhdl/specials: allow setting memory name
|
2013-02-25 23:14:03 +01:00 |
|
Sebastien Bourdeauducq
|
425de02f42
|
uio/ioo: fix specials
|
2013-02-25 23:13:38 +01:00 |
|
Sebastien Bourdeauducq
|
55ab01f928
|
fhdl/specials/Instance: _printintbool -> verilog_printexpr
|
2013-02-24 13:08:01 +01:00 |
|
Sebastien Bourdeauducq
|
a878db1e3c
|
genlib: clock domain crossing elements
|
2013-02-23 19:03:35 +01:00 |
|
Sebastien Bourdeauducq
|
7c4e6c35e5
|
fhdl/verilog: support special lowering and overrides
|
2013-02-23 19:03:16 +01:00 |
|
Sebastien Bourdeauducq
|
f9acee4e68
|
corelogic -> genlib
|
2013-02-22 23:19:37 +01:00 |
|
Sebastien Bourdeauducq
|
38664d6e16
|
fhdl: inline synthesis directive support
|
2013-02-22 19:10:02 +01:00 |
|
Sebastien Bourdeauducq
|
49cfba50fa
|
New 'specials' API
|
2013-02-22 17:56:35 +01:00 |
|
Sebastien Bourdeauducq
|
1b18194b1d
|
fhdl: TSTriple
|
2013-02-19 17:26:02 +01:00 |
|
Sebastien Bourdeauducq
|
dc93a231c6
|
fhdl: tristate support
|
2013-02-15 00:17:24 +01:00 |
|
Sebastien Bourdeauducq
|
63d399b6ad
|
fhdl/autofragment: from_attributes
|
2013-02-11 18:34:01 +01:00 |
|
Sebastien Bourdeauducq
|
92b67df41c
|
sim: default runner to Icarus Verilog
|
2013-02-09 17:04:53 +01:00 |
|
Sebastien Bourdeauducq
|
bd6856ba7a
|
flow/perftools: finish removing ActorNode
|
2013-02-09 17:03:48 +01:00 |
|
Sebastien Bourdeauducq
|
473fd20f8c
|
fhdl/structure: store clock domain name
|
2013-01-24 13:49:49 +01:00 |
|
Sebastien Bourdeauducq
|
3201554f76
|
fhdl/verilog: fix spurious clock/reset signals on multiple calls to convert()
|
2013-01-23 15:13:06 +01:00 |
|
Sebastien Bourdeauducq
|
314a6c7743
|
corelogic: complex arithmetic support
|
2013-01-05 14:18:36 +01:00 |
|
Sebastien Bourdeauducq
|
badba89686
|
fhdl: support nested statement lists
|
2013-01-05 14:18:15 +01:00 |
|
Sebastien Bourdeauducq
|
47f5fc70e4
|
pytholite: fix bug with constant assignment to register
|
2012-12-19 16:21:57 +01:00 |
|
Sebastien Bourdeauducq
|
9c65402fda
|
pytholite: prune unused registers
|
2012-12-19 16:03:05 +01:00 |
|
Sebastien Bourdeauducq
|
3fae6c8f03
|
Do not use super()
|
2012-12-18 14:54:33 +01:00 |
|
Sebastien Bourdeauducq
|
b06fbdedd6
|
fhdl/tools: bitreverse
|
2012-12-14 23:56:16 +01:00 |
|
Sebastien Bourdeauducq
|
1f350adf14
|
actorlib/sim/SimActor: do not drive busy low when generator yields None
|
2012-12-14 23:56:03 +01:00 |
|
Sebastien Bourdeauducq
|
a67f483f0f
|
Token: support idle_wait
|
2012-12-14 19:16:22 +01:00 |
|
Sebastien Bourdeauducq
|
6f99241585
|
Move Token to migen.flow.transactions
|
2012-12-14 15:55:38 +01:00 |
|
Sebastien Bourdeauducq
|
28b4d99d31
|
replace some forgotten is_abstract()
|
2012-12-12 22:36:45 +01:00 |
|
Sebastien Bourdeauducq
|
a7227d7d2b
|
Remove ActorNode
|
2012-12-12 22:20:48 +01:00 |
|
Sebastien Bourdeauducq
|
8163ed4828
|
Merge branch 'master' of github.com:milkymist/migen
|
2012-12-06 20:57:30 +01:00 |
|
Sebastien Bourdeauducq
|
483b821342
|
fhdl/structure: do not create Signal in Instance when parameter is int
|
2012-12-06 20:56:46 +01:00 |
|
Sebastien Bourdeauducq
|
280a87ea69
|
elsewhere: do not create interface in default param
|
2012-12-06 17:34:48 +01:00 |
|
Sebastien Bourdeauducq
|
62187aa23d
|
migen/bank: do not create interface in default param
|
2012-12-06 17:28:28 +01:00 |
|
Sebastien Bourdeauducq
|
c3fdf42825
|
bus/csr: add SRAM
|
2012-12-06 17:16:17 +01:00 |
|
Sebastien Bourdeauducq
|
e89c66bf14
|
bank/csrgen: interface -> bus
|
2012-12-06 17:15:34 +01:00 |
|
Sebastien Bourdeauducq
|
273d9d285b
|
bank/description: define reset value of read signal
|
2012-12-05 16:40:44 +01:00 |
|
Sebastien Bourdeauducq
|
34ce934809
|
actorlib/sim: drive busy high until generator is finished
|
2012-12-05 16:40:12 +01:00 |
|
Sebastien Bourdeauducq
|
4bcb39699b
|
bus/wishbone/sram: accept memories < 32 bits
|
2012-12-01 13:04:22 +01:00 |
|
Sebastien Bourdeauducq
|
523816982a
|
bus/wishbone: add SRAM
|
2012-12-01 12:59:09 +01:00 |
|
Sebastien Bourdeauducq
|
adb1565d7a
|
pytholite: fix bit width of selection signal
|
2012-11-30 17:07:32 +01:00 |
|
Sebastien Bourdeauducq
|
cfb23c442f
|
pytholite: support signed registers
|
2012-11-30 17:07:12 +01:00 |
|
Sebastien Bourdeauducq
|
7093939309
|
corelogic/roundrobin: fix request width (again)
|
2012-11-29 23:47:51 +01:00 |
|
Sebastien Bourdeauducq
|
31c722f993
|
corelogic/roundrobin: fix request width
|
2012-11-29 23:47:08 +01:00 |
|
Sebastien Bourdeauducq
|
70e97e0456
|
Fix various errors from new bitwidth/signedness system conversion
|
2012-11-29 23:36:55 +01:00 |
|
Sebastien Bourdeauducq
|
261166d92b
|
fhdl/verilog: make signal behave as integers in arithmetic (MyHDL style)
See http://jandecaluwe.com/hdldesign/counting.html
|
2012-11-29 22:59:54 +01:00 |
|
Sebastien Bourdeauducq
|
55d143a454
|
fhdl/structure: add unary minus
|
2012-11-29 22:52:57 +01:00 |
|
Sebastien Bourdeauducq
|
d8e478efee
|
Replace Signal(bits_for(... with Signal(max=...
|
2012-11-29 21:53:36 +01:00 |
|
Sebastien Bourdeauducq
|
50ed73c937
|
New specification for width and signedness
|
2012-11-29 21:22:38 +01:00 |
|
Sebastien Bourdeauducq
|
6eebfce44a
|
Refactor Case
|
2012-11-29 01:11:15 +01:00 |
|
Sebastien Bourdeauducq
|
070652cc39
|
pytholite/reg: use source id in dictionary
|
2012-11-29 00:09:35 +01:00 |
|
Sebastien Bourdeauducq
|
fee22a4631
|
Remove Constant
|
2012-11-28 23:18:43 +01:00 |
|
Sebastien Bourdeauducq
|
59831e0485
|
fhdl/structure: improved bits_for function
|
2012-11-28 18:39:44 +01:00 |
|
Sebastien Bourdeauducq
|
11b1e53224
|
visit/NodeTransformer: copy most nodes
|
2012-11-28 17:50:55 +01:00 |
|
Sebastien Bourdeauducq
|
a2bcbfdf8f
|
fhdl/tools: use NodeTransformer to lower arrays
|
2012-11-28 17:46:15 +01:00 |
|
Sebastien Bourdeauducq
|
3bc15024ac
|
fhdl/tools: use NodeVisitor
|
2012-11-26 21:40:23 +01:00 |
|
Sebastien Bourdeauducq
|
e3a983d731
|
Remove unroll
|
2012-11-26 20:07:48 +01:00 |
|
Sebastien Bourdeauducq
|
1460f069f6
|
fhdl/structure: remove deprecated MemoryPort
|
2012-11-26 19:36:43 +01:00 |
|
Sebastien Bourdeauducq
|
5183774ec8
|
bus/wishbone2asmi: do not use MemoryPort
|
2012-11-26 19:14:59 +01:00 |
|
Sebastien Bourdeauducq
|
fc85ca53ad
|
actorlib/spi: do not use MemoryPort
|
2012-11-26 18:27:59 +01:00 |
|
Sebastien Bourdeauducq
|
dac0d11e52
|
actorlib/sim: Dumper
|
2012-11-24 00:00:07 +01:00 |
|
Sebastien Bourdeauducq
|
27d87c9412
|
fhdl/structure: disable we_granularity when larger than width
|
2012-11-23 23:08:12 +01:00 |
|
Sebastien Bourdeauducq
|
d2c61e6a90
|
sim/generic/multiread: do not return spurious items
|
2012-11-23 23:07:25 +01:00 |
|
Sebastien Bourdeauducq
|
74721b206f
|
pytholite: fix import of _Slice
|
2012-11-23 21:20:18 +01:00 |
|
Sebastien Bourdeauducq
|
95122bb778
|
pytholite/io: support memory
|
2012-11-23 20:36:09 +01:00 |
|
Sebastien Bourdeauducq
|
f42683b71e
|
fhdl/structure/Memory: fix we width
|
2012-11-23 19:21:52 +01:00 |
|
Sebastien Bourdeauducq
|
0f6215a13a
|
fhdl/structure: add Memory.get_port API
|
2012-11-23 19:17:49 +01:00 |
|
Sebastien Bourdeauducq
|
9d3e218863
|
fhdl: use object creation counter (HUID) as hash. This finally makes the generated code textually the same across runs.
|
2012-11-23 18:38:03 +01:00 |
|
Sebastien Bourdeauducq
|
3971600917
|
fhdl/structure: use sets for memories and instance collections
|
2012-11-23 17:20:08 +01:00 |
|
Sebastien Bourdeauducq
|
f3efd74dfd
|
uio: support memories
|
2012-11-23 16:23:24 +01:00 |
|
Sebastien Bourdeauducq
|
ab31b4d99c
|
bus: memory initiator
|
2012-11-23 16:22:50 +01:00 |
|
Sebastien Bourdeauducq
|
0b7dd7bdce
|
pytholite/io: fix Wishbone writes + support sel attribute
|
2012-11-23 13:40:46 +01:00 |
|
Sebastien Bourdeauducq
|
4c216d8f11
|
pytholite/io: support Wishbone reads
|
2012-11-23 13:09:55 +01:00 |
|
Sebastien Bourdeauducq
|
0b24a2ff36
|
pytholite/io: support Wishbone writes
|
2012-11-23 12:41:50 +01:00 |
|
Sebastien Bourdeauducq
|
f098c5c695
|
pytholite/compiler: pass keyword arguments to gen_io
|
2012-11-23 12:40:57 +01:00 |
|
Sebastien Bourdeauducq
|
51e2e6ecd0
|
fhdl/verilog: remove empty cases
|
2012-11-18 16:32:51 +01:00 |
|
Sebastien Bourdeauducq
|
89643bc434
|
sim/ipc/Message: convert values
|
2012-11-17 23:19:40 +01:00 |
|
Sebastien Bourdeauducq
|
e92af9de59
|
pytholite/transel: use python3-compatible comparison methods
|
2012-11-17 23:16:07 +01:00 |
|
Sebastien Bourdeauducq
|
b6b4c5d70e
|
uio/ioo: fix UnifiedIOSimulation
|
2012-11-17 22:25:42 +01:00 |
|
Sebastien Bourdeauducq
|
1cabcb3c3f
|
uio: support generator trampolining in simulation
|
2012-11-17 19:59:22 +01:00 |
|
Sebastien Bourdeauducq
|
be68ecfc72
|
uio: add simulation I/O object
|
2012-11-17 19:55:33 +01:00 |
|
Sebastien Bourdeauducq
|
7add4c6f3c
|
uio: unified I/O object
|
2012-11-17 19:54:50 +01:00 |
|
Sebastien Bourdeauducq
|
d10df1a8ab
|
actorlib/sim: swap TokenExchanger parameters
|
2012-11-17 19:46:28 +01:00 |
|
Sebastien Bourdeauducq
|
d4baac6c0f
|
bus/csr: allow specifying existing interface
|
2012-11-17 19:44:25 +01:00 |
|
Sebastien Bourdeauducq
|
86090e1cbd
|
bus/asmibus: swap port position to be consistent with wishbone API
|
2012-11-17 19:42:39 +01:00 |
|
Sebastien Bourdeauducq
|
ece786d6aa
|
bus/wishbone: allow specifying existing interface
|
2012-11-17 19:42:06 +01:00 |
|
Sebastien Bourdeauducq
|
d0d4c48098
|
bus/transactions: add busname parameter
|
2012-11-17 19:36:08 +01:00 |
|
Sebastien Bourdeauducq
|
897a2e3f9c
|
actorlib/sim: split TokenExchanger
|
2012-11-17 14:15:51 +01:00 |
|
Sebastien Bourdeauducq
|
eb156af20c
|
pytholite/io: support token pull
|
2012-11-16 23:48:41 +01:00 |
|
Sebastien Bourdeauducq
|
dd9a102a78
|
pytholite/io: support token push
|
2012-11-16 19:24:45 +01:00 |
|
Sebastien Bourdeauducq
|
bf5ce8dc20
|
pytholite: move expression and register handling to separate modules
|
2012-11-11 23:48:23 +01:00 |
|
Sebastien Bourdeauducq
|
f59fd69e34
|
pytholite/compiler: recognize composite I/O pattern
|
2012-11-11 18:03:16 +01:00 |
|
Sebastien Bourdeauducq
|
0b5652bb79
|
pytholite/compiler: visit_assign_special
|
2012-11-11 15:52:06 +01:00 |
|
Sebastien Bourdeauducq
|
687d18a150
|
pytholite: move FSM management to separate module
|
2012-11-11 14:30:25 +01:00 |
|
Sebastien Bourdeauducq
|
409a5570e4
|
pytholite/compiler: refactor visit_block
|
2012-11-11 14:17:52 +01:00 |
|
Sebastien Bourdeauducq
|
fb63698ef4
|
pytholite/compiler: clean up visit_statement
|
2012-11-10 23:30:14 +01:00 |
|
Sebastien Bourdeauducq
|
6ebd1e4503
|
pytholite: forward 'yield call' statements to io module
|
2012-11-10 22:59:14 +01:00 |
|
Sebastien Bourdeauducq
|
48acb1bcfd
|
pytholite: introduce io module
|
2012-11-10 21:51:19 +01:00 |
|
Sebastien Bourdeauducq
|
6776f06a42
|
pytholite/compiler: support bitslice
|
2012-11-10 18:04:05 +01:00 |
|
Sebastien Bourdeauducq
|
37f113c3ea
|
pytholite/compiler: support range(constants) in for loops
|
2012-11-10 15:26:13 +01:00 |
|
Sebastien Bourdeauducq
|
370bab1190
|
pytholite/compiler: cleanup print statements
|
2012-11-10 15:10:57 +01:00 |
|
Sebastien Bourdeauducq
|
39c7dc7d63
|
pytholite/compiler: support for loops (iterating on lists only)
|
2012-11-10 15:02:55 +01:00 |
|
Sebastien Bourdeauducq
|
93db3edd00
|
pytholite/compiler: support while loops
|
2012-11-10 14:37:33 +01:00 |