Commit Graph

53 Commits

Author SHA1 Message Date
Florent Kermarrec 27b1dd7d9e litescope/core/port: fix EdgeDetector CSRs names 2015-08-24 19:40:53 +02:00
Florent Kermarrec fd31e6ae61 litescope/core/port: fix LiteScopeEdgeDetector (refactoring issues) 2015-08-24 18:23:38 +02:00
Florent Kermarrec 63538a7d04 litecores: add -Ob option to make.py (allow to build with yosys for example) 2015-08-19 01:17:37 +02:00
Florent Kermarrec d9b15e6ef6 cores: replace Timeout with new WaitTimer 2015-05-12 16:14:38 +02:00
Florent Kermarrec a99aa9c7fd uart: rename wishbone to bridge 2015-05-09 16:24:28 +02:00
Florent Kermarrec fb5397aa82 uart: remove litescope dependency for UARTWishboneBridge and remove frontend 2015-05-09 16:08:20 +02:00
Florent Kermarrec 1761bfba8a litescope/frontend/wishbone: add support for packetized mode 2015-05-02 16:22:43 +02:00
Florent Kermarrec 3ebe877fd2 use similar names for wishbone bridges and move wishbone drivers to [core]/software 2015-05-02 16:22:30 +02:00
Florent Kermarrec 5e649a6577 litescope: add basic LiteScopeUSB2WishboneFTDIDriver (working but need to be optimized) 2015-05-01 20:45:04 +02:00
Florent Kermarrec c03c41eb77 litescope: rename host directory to software (to be coherent with others cores) 2015-05-01 20:45:02 +02:00
Florent Kermarrec cd3a51ada6 litescope: fix missing source ack on LiteScopeWishboneBridge 2015-05-01 20:44:57 +02:00
Florent Kermarrec 1281a463d6 litescope/bridge: create a generic wishbone bridge that can be used with different phys (the phy needs to provide a sink/source with 8bits data).
- we can now pass a phy to LiteScopeWishboneBridge
- LiteScopeUART2Wishbone is only a specific LiteScopeWishboneBridge
- UART mux is removed since complicated and no longer useful (we can now create easily virtual UART over Ethernet, USB or PCIe) or simply add another UART for debug.
2015-05-01 17:51:18 +02:00
Florent Kermarrec 23126415d3 litescope: use full name in io.py 2015-05-01 17:49:31 +02:00
Florent Kermarrec ff2d1d9383 litescope: fix read in reg.py 2015-04-20 08:16:31 +02:00
Florent Kermarrec 4c0d9f5f36 litescope: remove repeat mode on drivers (not useful) and cleanup 2015-04-18 15:37:38 +02:00
Florent Kermarrec 5a930fe7cf lite* cores: changes permissions (+x) on make.py files and on litepcie init.sh file 2015-04-18 08:51:59 -04:00
Florent Kermarrec 341f635a85 litescope: add PCIe driver (mmap/Sysfs) and use it on litepcie example design 2015-04-18 13:58:20 +02:00
Florent Kermarrec 312f302d36 litescope/examples_designs: add build directory 2015-04-13 14:53:17 +02:00
Florent Kermarrec 40abd66d69 litescope: more pep8 (when convenient), should be almost OK 2015-04-13 13:56:24 +02:00
Florent Kermarrec 4cdb0ddf3a litescope: pep8 (E265) 2015-04-13 13:46:06 +02:00
Florent Kermarrec 8f9bd24f6f litescope: pep8 (E261, E271) 2015-04-13 13:40:30 +02:00
Florent Kermarrec eb58f45b31 litescope: pep8 (W292) 2015-04-13 13:38:35 +02:00
Florent Kermarrec f16623d548 litescope: pep8 (E225) 2015-04-13 13:37:46 +02:00
Florent Kermarrec 7e37d7b6d0 litescope: pep8 (E222) 2015-04-13 13:29:41 +02:00
Florent Kermarrec 651e228e22 litescope: pep8 (E401) 2015-04-13 13:28:47 +02:00
Florent Kermarrec 49dcf8d831 litescope: pep8 (E203) 2015-04-13 13:25:27 +02:00
Florent Kermarrec 51ca259bdb litescope: pep8 (E231) 2015-04-13 13:23:48 +02:00
Florent Kermarrec 67b4da8ecf litescope: pep8 (E201) 2015-04-13 13:20:13 +02:00
Florent Kermarrec 13e4d7c525 litescope: pep8 (E302) 2015-04-13 13:18:21 +02:00
Florent Kermarrec 1328328540 litescope: pep8 (replace tabs with spaces) 2015-04-13 13:09:44 +02:00
Florent Kermarrec b437dc3185 remove use of _r prefix on CSRs 2015-04-02 12:18:43 +02:00
Florent Kermarrec f65c0a3c95 adapt LiteScope to new SoC 2015-04-01 22:46:24 +02:00
Florent Kermarrec 236ea0f572 liteeth: use bios ip_address in example designs 2015-03-18 18:18:43 +01:00
Florent Kermarrec 70f1f96fda litescope/drivers: do not build regs when addrmap is None 2015-03-17 16:04:31 +01:00
Florent Kermarrec a266deb58e LiteXXX cores: fix frequency print in test/test_regs.py 2015-03-17 16:01:25 +01:00
Florent Kermarrec d2cb41bc63 LiteXXX cores: convert port parameter to int if is digit in test/make.py 2015-03-17 15:58:21 +01:00
Florent Kermarrec a874f85854 litescope: use CRG from Migen 2015-03-17 11:52:54 +01:00
Florent Kermarrec 52f1c45407 LiteXXX cores: fix test_reg.py 2015-03-04 23:13:14 +01:00
Florent Kermarrec 1d4dc45436 LiteXXX cores: use format in prints 2015-03-03 10:29:28 +01:00
Florent Kermarrec 096e95cb59 uart: use data instead of d on endpoint's layouts (coherency with others cores) 2015-03-01 16:56:48 +01:00
Florent Kermarrec 649cdeb265 liteXXX cores: use new uart and import FlipFlop/Counter/Timeout from Migen 2015-03-01 16:48:41 +01:00
Florent Kermarrec c21a7956c8 liteXXX cores: remove Identifier duplication 2015-03-01 11:24:58 +01:00
Florent Kermarrec 67ca0da1d9 liteXXX cores: share same methodology for on-board tests 2015-03-01 11:21:12 +01:00
Florent Kermarrec 32fce11edf litescope: avoid uart code duplication 2015-03-01 10:07:55 +01:00
Florent Kermarrec b32a0e6f9e liteeth: create example design derived from SoC that can be used on all targets with Ethernet pins 2015-02-28 23:33:00 +01:00
Florent Kermarrec b34be816ec liteXXX cores: remove setup.py and relative paths (we will install misolib of use PYTHON_PATH) 2015-02-28 22:23:48 +01:00
Florent Kermarrec 5c43d4d091 litescope: create example design derived from SoC that can be used on all targets 2015-02-28 22:19:24 +01:00
Florent Kermarrec 0fd1b9df8d liteXXX cores: remove redefinition of get_csr_csv 2015-02-28 21:45:05 +01:00
Florent Kermarrec 5bd1ab7fa1 liteXXX cores: update README and doc 2015-02-28 21:40:59 +01:00
Florent Kermarrec 69e869893d remane GenSoC to SoC (more coherent and we will add support for multiple SoCs with their own Wisbbone/CSR buses in the future) 2015-02-28 11:36:15 +01:00