Hardware
/
litex
mirror of https://github.com/enjoy-digital/litex.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity
1,555 Commits 42 Branches 14 Tags 30 MiB
Commit Graph

370 Commits

Author SHA1 Message Date
Florent Kermarrec 8e04ef7b95 test minicon with de0nano (OK) and fix missing self in gensoc 2015-02-27 20:00:16 +01:00
Florent Kermarrec f1200d6388 gensoc: move I/O for rom initialization to make.py 2015-02-27 19:48:07 +01:00
Florent Kermarrec e07e124118 sdram: import dfi, lasmibus, wishbone2lasmi from Migen in sdram/bus dir 
We will maybe move things, but at least it's in MiSoC now
 2015-02-27 17:07:44 +01:00
Florent Kermarrec 07b9cabd0d gensoc: make it more generic (a SoC does not necessarily have a CPU) 2015-02-27 16:39:00 +01:00
Florent Kermarrec be0eb8d265 use cachesize reported in wishbone2lasmi 2015-02-27 14:13:38 +01:00
Florent Kermarrec 9814001c79 create cpu dir and move lm32/mor1kx in it 2015-02-27 10:51:03 +01:00
Florent Kermarrec 9f636f7985 move memtest to sdram 2015-02-27 10:47:54 +01:00
Florent Kermarrec b817cf49b3 replace self._r_register by self._register in all CSR declaration 2015-02-27 10:36:09 +01:00
Florent Kermarrec 77a6f580e2 gensoc: add check_cpu_memory_region and check_csr_region to detect csr and mem regions conflicts 2015-02-27 10:23:02 +01:00
Florent Kermarrec 617bc70d7f liteeth: move doc 2015-02-27 09:15:54 +01:00
Robert Jordens c9ed38dec8 gensoc: missing self. 2015-02-26 21:32:11 -07:00
Florent Kermarrec 09fbbca53e gensoc: cpus now directly add their verilog sources 2015-02-26 20:49:21 +01:00
Florent Kermarrec 5e8a0c496d gensoc: add mem_map and mem_decoder to avoid duplications 2015-02-26 20:12:27 +01:00
Florent Kermarrec 5ac5ffe359 gensoc: get platform_id from platform 2015-02-26 19:07:19 +01:00
Florent Kermarrec 02b3f51382 liteeth: fix example_designs generation 2015-02-26 10:23:38 +01:00
Florent Kermarrec 00862a383c liteeth: fix import (from liteeth --> from misoclib.liteeth) 2015-02-26 09:48:37 +01:00
Florent Kermarrec 60effe1d95 move files to liteeeth and create example_designs directory 2015-02-26 09:35:14 +01:00
Sebastien Bourdeauducq 658cb0e405 merge liteeth 2015-02-25 10:35:39 -07:00
Sebastien Bourdeauducq 8015d12692 move files for misoc integration 2015-02-25 10:34:11 -07:00
Florent Kermarrec 0a38b8c74a add LiteX external core and remove ethmac 2015-02-18 10:43:44 -07:00
Florent Kermarrec 9ebb8f8022 remove verilog and move mxcrg.v to misoclib/mxcrg 2015-02-18 10:40:30 -07:00
Florent Kermarrec 5500c41915 move lm32/mor1kx submodules to extcores 2015-02-18 10:39:18 -07:00
Florent Kermarrec 4c9554b65c gensoc: call do_exit after SoC is built 2015-02-18 10:38:14 -07:00
Florent Kermarrec da13bd536e gensoc: add csr_data_width and csr_address_width as parameters In some case we want to have mode than 32 CSR or and csr_data_width != 8 2015-02-14 03:24:23 -08:00
Florent Kermarrec 9bb7e6d0ab ethmac: improve testbenchs 2014-12-21 17:37:25 +08:00
Sebastien Bourdeauducq aac34f011f gensoc: support user-defined CSR regions 2014-11-30 22:29:26 +08:00
Sebastien Bourdeauducq 8ae3a00a94 gensoc: simplify WB address decoding 2014-11-30 22:05:51 +08:00
Sebastien Bourdeauducq 4189440eef minicon: small simplifications 2014-11-28 08:28:39 +08:00
Yann Sionneau edb1622668 spiflash: BB write support 2014-11-27 23:10:39 +08:00
Sebastien Bourdeauducq bab6bb7c4a gensoc: fix align 2014-11-27 23:05:36 +08:00
Sebastien Bourdeauducq 2cd80990e4 minicon: fix use of phy phases 2014-11-27 22:13:17 +08:00
Sebastien Bourdeauducq 8418ccafdc minicon: remove unused signals and fix indent 2014-11-27 22:12:05 +08:00
Yann Sionneau cf92821fcf Refactor directory hierarchy of sdram phys and controllers 2014-11-27 22:09:10 +08:00
Yann Sionneau f33b285af1 Minicon: small SDRAM controller 2014-11-27 22:09:03 +08:00
Florent Kermarrec 5202f89db1 ethmac/last_be: remove fake signal (fixed in Migen) 2014-11-21 14:48:17 -08:00
Sebastien Bourdeauducq b7028848b2 ethmac: use new EndpointDescription API 2014-11-20 22:32:32 -08:00
Sebastien Bourdeauducq 33530e0921 ethmac: style/renaming 2014-11-20 18:01:48 -08:00
Florent Kermarec 603c2641bb new Ethernet MAC 2014-11-20 16:47:22 -08:00
Florent Kermarrec 8e4b89849c use new direct access on endpoints 2014-10-20 23:13:37 +08:00
Florent Kermarrec 34ed315a48 remove trailing whitespaces 2014-10-17 17:14:40 +08:00
Sebastien Bourdeauducq e53fb88b85 uart: minor cleanup and fix 2014-10-10 15:33:27 +08:00
Florent Kermarrec 5e5f436aa6 uart: split it and use dataflow 
This make the code easier to understand and allow the reuse of UARTRX & UARTTX
on designs without CPU (e.g miscope).
 2014-10-10 15:24:47 +08:00
Florent Kermarrec c0c17030fd spi_flash: simplify usage by removing cmd, cmd_width, addr_width parameters 2014-09-04 15:23:39 +08:00
Sebastien Bourdeauducq 36434b62f0 sdram: merge DFII_PIX_RDDATA_SIZE and DFII_PIX_WRDATA_SIZE 2014-09-03 15:02:38 +08:00
Sebastien Bourdeauducq a7b4550e59 sdramphy/initsequence: cleanup and expose DDR3 MR1 value 2014-09-03 14:21:30 +08:00
Florent Kermarrec 114890ee80 sdramphy/initsequence: clean up mr1/mr2 computation on DDR3 and enable Dynamic ODT 2014-09-02 10:54:29 +08:00
Sebastien Bourdeauducq 2234f50223 k7ddrphy: add bitslip control for incoming DQ 2014-09-01 19:54:39 +08:00
Sebastien Bourdeauducq 5483b37c8f k7ddrphy: write leveling and read calibration support 2014-08-31 21:54:28 +08:00
Sebastien Bourdeauducq 19abe2b888 k7ddrphy: do not register T at SERDES (fixes timing problem) 2014-08-31 21:53:35 +08:00
Sebastien Bourdeauducq 541e5abbc7 k7ddrphy: update comment 2014-08-22 19:02:57 +08:00
Sebastien Bourdeauducq 66fe45ba96 k7ddrphy: decrease CAS latency to account for cmd/data flight time 2014-08-22 18:46:01 +08:00
Sebastien Bourdeauducq b94647ab16 k7ddrphy: suppress idiotic bitgen warning about ISERDES IOBDELAY parameter 2014-08-22 18:45:25 +08:00
Florent Kermarrec 1c381acc6f k7ddrphy: fix read_latency (CL is 2 sys_clk since we use quarter rate) 2014-08-14 22:46:06 +08:00
Florent Kermarrec acbba37f5f k7ddrphy: set bitslip to 0 on ISERDESE2 (needed at least for sim) 2014-08-14 22:46:06 +08:00
Florent Kermarrec 2e4bfe154f k7ddrphy: add ODELAYE2 on dm path to match dq path (ODELAYE2 even configure with a delay of 0 generates a delay) 2014-08-14 22:46:06 +08:00
Florent Kermarrec bb85f29f91 k7ddrphy: fix write_latency and take care of OSERDESE2 latency on oe 2014-08-14 22:46:06 +08:00
Florent Kermarrec 85b29c883a sdramphy/initsequence: fix and add format_mr0 function 2014-08-14 14:17:54 +08:00
Florent Kermarrec 9844c25df9 k7ddrphy: add SERDES reset 2014-08-14 14:16:41 +08:00
Florent Kermarrec 194a5a0491 lasmicon: fix reset_n level 2014-08-14 14:15:48 +08:00
Sebastien Bourdeauducq c8dd4d2b40 k7ddrphy: send rddata_valid on all phases 2014-08-09 11:00:13 +08:00
Sebastien Bourdeauducq 8deadc5760 dfii: drive ODT and RESET_N 2014-08-08 21:56:35 +08:00
Sebastien Bourdeauducq 1322c0484b lasmicon: drive ODT and RESET_N 2014-08-08 21:55:34 +08:00
Sebastien Bourdeauducq 0550cbb3ce lasmicon: add CWL to PHY settings 2014-08-08 21:55:12 +08:00
Sebastien Bourdeauducq 777ebb7875 sdramphy/gensdrphy: fix rddata_en generation 2014-08-08 21:41:07 +08:00
Sebastien Bourdeauducq a2c7ff4c0c sdramphy: initial K7 DDR3 support 2014-08-08 21:28:26 +08:00
Florent Kermarrec 293ac09673 sdramphy/bios: make sdrrd/sdrwr generic 2014-08-08 19:25:10 +08:00
Sebastien Bourdeauducq cfc37a3fa5 sdramphy/initsequence: rewrite DDR3 initialization sequence 2014-08-08 19:15:05 +08:00
Sebastien Bourdeauducq e8db842538 s6ddrphy: fix DFI interface data width computation 2014-08-08 19:14:15 +08:00
Sebastien Bourdeauducq efb2466c7e gensoc: add id for KC705 2014-08-06 23:53:51 +08:00
Florent Kermarrec d1ff43faa7 gensoc/cpuif: do not generate access functions for registers > 64 bits 2014-08-04 22:38:19 +08:00
Sebastien Bourdeauducq 213cb43ae5 Keep only basic SoC designs in MiSoC 2014-08-03 12:30:15 +08:00
Florent Kermarrec 25b3aff6f1 sdramphy: add init sequence for DDR3 2014-07-31 10:29:32 +08:00
Yann Sionneau 32171da46d Better UART baudrate generator, and testbench 
This enables high speed (tested to 4Mbps) operation.
 2014-07-31 10:24:52 +08:00
Florent Kermarrec d4833cb3dc cpuif: remove limitations on csr data_width 2014-06-28 17:39:55 +02:00
Robert Jordens 81ed92d3b9 spiflash: redundant slice 2014-05-24 10:39:07 +02:00
Florent Kermarrec f4c0648289 gensdrphy: fix dm generation 2014-05-21 21:16:06 +02:00
Florent Kermarrec 54339a6d5b gensdrphy: fix memtype and change phase shift in comments. 2014-05-16 16:52:24 +02:00
Sebastien Bourdeauducq 6298624f98 sdramphy: remove fixed parameters 2014-05-14 16:08:40 +02:00
Sebastien Bourdeauducq 1c08aeb21c Initial mor1kx (OpenRISC) support 
Based on milkymist-ng-mor1kx by Stefan Kristiansson
 2014-05-14 10:24:56 +02:00
Florent Kermarrec 774464155a gensdrphy: clean up and implement data mask 2014-05-01 16:17:50 +02:00
Robert Jordens 3ab9f234d0 gensdrphy: use 'dm' not 'dqm' (follow s6ddrphy and majority of platforms) 2014-04-25 10:38:57 +02:00
Florent Kermarrec 1adceb8276 sdramphy: move and clean up s6ddrphy, add generic SDRAM PHY 2014-04-17 19:38:25 +02:00
Sebastien Bourdeauducq 9e784fc82c Generate mem.h from SoC description 2014-02-21 17:55:05 +01:00
Sebastien Bourdeauducq bdb47e7977 dvisampler: replace parity with sof 2014-02-13 22:45:27 +01:00
Sebastien Bourdeauducq 42c25f44ad videostream: add downscaler core + test 2014-02-10 00:12:57 +01:00
Sebastien Bourdeauducq 2a3803d3a1 videostream: add single chopper 2014-02-09 00:53:30 +01:00
Sebastien Bourdeauducq b6a00e86e4 videostream: add compacter and packer 2014-02-08 18:39:01 +01:00
Sebastien Bourdeauducq 25acf17312 Refresh testbenches and convert to new API 2014-01-28 13:50:01 +01:00
Sebastien Bourdeauducq e464935119 downscaler: add chopper module 2014-01-21 15:56:51 +01:00
Sebastien Bourdeauducq ad974a07ef gensoc: support for user-defined UART and add default values for SRAM and L2 sizes 2014-01-06 22:12:42 +01:00
Sebastien Bourdeauducq c95b9d6d76 gensoc: use add_verilog_include_path 2013-12-12 23:17:16 +01:00
Sebastien Bourdeauducq 55a39269d2 gpio: add InOut 2013-12-06 00:06:53 +01:00
Sebastien Bourdeauducq cfb9074755 norflash16: fix LSB 2013-11-30 23:06:51 +01:00
Sebastien Bourdeauducq 352919d17e norflash: add support for writes 2013-11-30 20:37:56 +01:00
Robert Jordens 5953f901c8 spiflash: add read-only variable data width spi flash 
Signed-off-by: Robert Jordens <jordens@gmail.com>
 2013-11-25 14:23:55 +01:00
Sebastien Bourdeauducq 96600ad9d7 set LM32 reset address 2013-11-25 12:09:16 +01:00
Sebastien Bourdeauducq 7459a849ee IntegratedBIOS: read only 2013-11-25 10:25:05 +01:00
Sebastien Bourdeauducq 78cd7a288e move integrated BIOS code to gensoc 2013-11-25 10:22:14 +01:00
Sebastien Bourdeauducq b212e0279d gensoc: add Papilio Pro ID 2013-11-24 23:50:33 +01:00
Sebastien Bourdeauducq 257185cc9c rename create_sdram_modules and add register_rom 2013-11-24 20:16:19 +01:00
Sebastien Bourdeauducq fca0b968e7 generate linker memory map, move all generated files into the same folder 2013-11-24 19:50:17 +01:00
Sebastien Bourdeauducq fdff1ae5f8 make build system more generic 2013-11-24 13:37:32 +01:00
Sebastien Bourdeauducq 4a3a1d02e9 modularize SoC integration 2013-11-24 10:30:02 +01:00
Sebastien Bourdeauducq 7496ba6360 framebuffer: fix resynchronization after resolution change 2013-11-21 00:33:22 +01:00
Sebastien Bourdeauducq 96fcb3574e Revert "framebuffer: reset VTG" 
This reverts commit 6cb18f5ce3.

Conflicts:
	misoclib/framebuffer/__init__.py
	misoclib/framebuffer/format.py
 2013-11-19 23:48:00 +01:00
Sebastien Bourdeauducq 2eabf97147 dvisampler: transfer the last word in frames correctly 2013-11-19 23:38:48 +01:00
Sebastien Bourdeauducq de76e91147 framebuffer: expose PLL DRP to CSR 2013-11-18 20:32:33 +01:00
Sebastien Bourdeauducq 9e883b8b02 dvisampler: expose PLL DRP to CSR 2013-11-18 20:32:21 +01:00
Sebastien Bourdeauducq 4cfcda6c8c framebuffer: unpack memory words in pixel clock domain for better perf 2013-11-17 23:41:18 +01:00
Sebastien Bourdeauducq c3d0985fb2 add L2 cache size in identifier + function to flush L2 2013-11-16 16:27:21 +01:00
Sebastien Bourdeauducq 6f990a017e dvisampler: pack pixels in pixel clock domain to improve performance 2013-11-16 13:53:26 +01:00
Sebastien Bourdeauducq 6cb18f5ce3 framebuffer: reset VTG 2013-11-15 11:25:07 +01:00
Sebastien Bourdeauducq 34e8e8c259 dvisampler: update address CSR at end of DMA 2013-11-13 18:57:10 +01:00
Sebastien Bourdeauducq 15499560b5 cpuif: add memories to csr.h 2013-11-11 16:53:00 +01:00
Sebastien Bourdeauducq 75d25af3aa cosmetic changes 2013-11-10 16:12:24 +01:00
Robert Jordens 31ec33dbad s6ddrphy: use shorter Instance argument notation 
Signed-off-by: Robert Jordens <jordens@gmail.com>
 2013-11-10 12:52:03 +01:00
Robert Jordens c1e5683ba2 s6ddrphy: drop unused outputs, shortens verilog and produces more readable warnings 
Signed-off-by: Robert Jordens <jordens@gmail.com>
 2013-11-10 11:13:36 +01:00
Robert Jordens 05944cf909 cpuif.py: add _ADDR and _SIZE defines for each register 
Signed-off-by: Robert Jordens <jordens@gmail.com>
 2013-11-10 10:44:39 +01:00
Sebastien Bourdeauducq d7a4d8b66e use git commit id as version 2013-11-09 16:38:44 +01:00
Sebastien Bourdeauducq 0b881d934f rename milkymist-ng to MiSoC 2013-11-09 15:27:32 +01:00