Florent Kermarrec
|
5301a1776d
|
targets: remove USBSoC from minispartan6 (example available here: https://github.com/enjoy-digital/scarab-soc)
|
2015-09-07 12:47:40 +02:00 |
Florent Kermarrec
|
158fbe49ac
|
sdram/phy/s6ddrphy: rename S6DDRPHY to S6HalfRateDDRPHY and use ORed wrdata_en/rddata_en (the controller already manages that)
|
2015-08-22 11:47:26 +02:00 |
Florent Kermarrec
|
ce11b30140
|
misoclib: integrate mxcrg.py in mlabs_video target, remove others directory
we should also get rid of mxcrg.v (similar to what is done on papilio or pipstrello)
|
2015-07-24 23:16:45 +02:00 |
Robert Jordens
|
2150e6cfef
|
pipistrello: run at 83+1/3 MHz, cleanup CRG
|
2015-06-22 18:56:57 -06:00 |
Florent Kermarrec
|
c98bd9fd79
|
rename shadow_address to shadow_base (more appropriate) and use | instead of + (as done in artiq)
|
2015-05-02 17:07:58 +02:00 |
Florent Kermarrec
|
63b8797978
|
liteeth: move mac to core
|
2015-05-02 16:22:35 +02:00 |
Florent Kermarrec
|
a4617014f4
|
cores: avoid having too much directories when possible (for simple cores or cores contained in a single file)
|
2015-05-02 16:22:33 +02:00 |
Zach Smith
|
1832f27220
|
targets/pipistrello: add flash sizes
|
2015-05-02 09:59:24 +08:00 |
Florent Kermarrec
|
23ba1ccb52
|
targets/minispartan6: add USBSoC (working, should also be usable on pipistrello)
|
2015-05-01 16:22:45 +02:00 |
Sebastien Bourdeauducq
|
1d9771f574
|
spiflash: use SoC defines, add write_to_flash function
|
2015-04-27 13:42:32 +08:00 |
Florent Kermarrec
|
0b1a2e1022
|
liteeth: do MII/GMII detection in gateware for gmii_mii phy
|
2015-04-26 18:08:07 +02:00 |
Florent Kermarrec
|
5b48e7bb52
|
liteeth: finish with_preamble_crc vs with_hw_preamble_crc renaming
|
2015-04-24 11:30:35 +02:00 |
Florent Kermarrec
|
93de581931
|
soc: add shadow_address parameter
When don't necessary want to have shadow memories and be able to start CSR at address 0x00000000(for example with an X86 CPU)
|
2015-04-17 13:42:29 +02:00 |
Florent Kermarrec
|
2ccb5655c9
|
global: more pep8
we will have to continue the work... volunteers are welcome :)
|
2015-04-13 18:02:26 +02:00 |
Florent Kermarrec
|
fc68d915c1
|
global: pep8 (E261, E271)
|
2015-04-13 17:16:12 +02:00 |
Florent Kermarrec
|
f68423f423
|
global: pep8 (E302)
|
2015-04-13 16:47:22 +02:00 |
Florent Kermarrec
|
d9e09707ae
|
global: pep8 (replace tabs with spaces)
|
2015-04-13 16:19:55 +02:00 |
Robert Jordens
|
d6c19858fa
|
s6ddrphy: redo phase_sel, get rid of CLOCK_DEDICATED_ROUTE
|
2015-04-10 16:12:29 +08:00 |
Sebastien Bourdeauducq
|
696819cc7f
|
move gpio from cpu.peripherals to com
|
2015-04-02 17:17:33 +08:00 |
Sebastien Bourdeauducq
|
369086a178
|
soc: simplify integrated memory parameters
|
2015-04-02 00:09:38 +08:00 |
Sebastien Bourdeauducq
|
980791e2b8
|
soc: remove ns function
|
2015-04-01 14:33:12 +08:00 |
Robert Jordens
|
54c14c7119
|
pipistrello: add por reset counter
* this is a temporary fix that should be removed once the
combination of bitstream-in-flash, mor1kx, bios-in-flash works
|
2015-03-27 19:18:11 +01:00 |
Florent Kermarrec
|
340014dbac
|
targets: revert use of integers in clocks/timings
|
2015-03-26 23:45:35 +01:00 |
Florent Kermarrec
|
ba8b24df57
|
sdram: pass module as phy parameter, define memtype in modules and only keep phy parameter in register_sdram_phy
|
2015-03-25 16:57:38 +01:00 |
Florent Kermarrec
|
a0ee0d8ff6
|
targets: add minispartan6 (SDRAM working)
|
2015-03-22 03:29:11 +01:00 |
Florent Kermarrec
|
d33729dda9
|
targets: pipistrello/ppro, fix stupid mistake 10ex --> 1ex...
|
2015-03-22 02:33:29 +01:00 |
Florent Kermarrec
|
cf17f06860
|
targets: fix CLKIN1_PERIOD on ppro and pipistrello
|
2015-03-22 00:30:21 +01:00 |
Florent Kermarrec
|
30c2521eb0
|
sdram: pass sdram_controller_settings to SDRAMSoC
|
2015-03-21 23:12:18 +01:00 |
Florent Kermarrec
|
70469e1f37
|
sdram: simplify the way we pass settings to controller and rename ramcon_type to sdram_controller_type (more explicit)
|
2015-03-21 21:32:39 +01:00 |
Florent Kermarrec
|
c55199deb9
|
misoclib/soc: add _integrated_ to cpu options to avoid confusion
|
2015-03-21 20:51:37 +01:00 |
Florent Kermarrec
|
711540e15c
|
targets/mlabs_video: rename sdram_module to sdram_modules to reflect that we have 2 modules sharing the same characteristics
|
2015-03-21 18:10:56 +01:00 |
Florent Kermarrec
|
1c0e306176
|
targets/kc705: rename sdram_module to sdram_modules to reflect that we have 8 modules sharing the same characteristics
|
2015-03-21 18:07:10 +01:00 |
Florent Kermarrec
|
52924ee1f2
|
sdram: define MT46V32M16/MT8JTF12864 and use it on pipistrello/kc705
|
2015-03-21 17:25:36 +01:00 |
Florent Kermarrec
|
fd2f8d4bb4
|
sdram: define MT46V32M16 and use it on m1/mixxeo
|
2015-03-21 17:04:58 +01:00 |
Florent Kermarrec
|
de2f1c31d5
|
sdram: create module.py to define SDRAM modules and use it on de0nano/ppro targets
|
2015-03-21 16:56:53 +01:00 |
Florent Kermarrec
|
6e4b7c6cfd
|
sdram: split sdram_timing in sdram_timing_settings/sdram_controller_settings
req_queue_size, read_time, write_time settings are not sdram_timing settings but sdram controller settings
|
2015-03-21 12:55:39 +01:00 |
Robert Jordens
|
ec465959d0
|
pipistrello: add user reset
apparently needed for flashed bitstream, xiped bios, mor1kx
|
2015-03-19 19:01:06 +01:00 |
Robert Jordens
|
a10875a3b7
|
pipistrello: fix flash, ddram pin naming
|
2015-03-19 19:01:06 +01:00 |
Florent Kermarrec
|
9f2e5cd7b6
|
targets/kc705: add external reset
|
2015-03-19 15:58:04 +01:00 |
Florent Kermarrec
|
cb4be52922
|
targets: add Lattice ECP3 versa
|
2015-03-17 19:09:43 +01:00 |
Florent Kermarrec
|
b2f32ad124
|
targets/simple: manual instantiation of CRG (automatic insertion works for BaseSoC but not for MiniSoC since this one define clock_domains)
|
2015-03-17 01:07:44 +01:00 |
Florent Kermarrec
|
28d04ec300
|
soc: rename with_sdram option to with_main_ram (with_sdram was confusing)
|
2015-03-14 00:49:19 +01:00 |
Sebastien Bourdeauducq
|
d09529d483
|
targets/simple: use mibuild default clock
|
2015-03-14 00:11:59 +01:00 |
Florent Kermarrec
|
1b72b81f9c
|
targets/simple: use new generic DifferentialInput
|
2015-03-12 18:36:04 +01:00 |
Florent Kermarrec
|
f18ae9b9fe
|
targets/simple: insert IBUFDS for Xilinx devices (not implemented for others vendors)
|
2015-03-12 17:25:01 +01:00 |
Florent Kermarrec
|
e133777450
|
targets/simple: add MiniSoC
|
2015-03-06 10:10:58 +01:00 |
Florent Kermarrec
|
95fa753149
|
liteeth: add phy autodetect function (phy can still be instanciated directly)
|
2015-03-06 10:10:34 +01:00 |
Florent Kermarrec
|
2b9397ff5b
|
targets: do not implement sdram if already provided by SoC (allow use of -Ot with_sdram = True)
|
2015-03-06 07:56:45 +01:00 |
Florent Kermarrec
|
0716dadaf2
|
targets: keep the SPI flash core even if with_rom is enabled, so that flash booting in the BIOS still works
|
2015-03-03 10:39:31 +01:00 |
Florent Kermarrec
|
02ef1dc95a
|
targets: fix mlabs_video FramebufferSoC
|
2015-03-02 18:38:43 +01:00 |