Hardware/litex
1
0
Fork 0
mirror of https://github.com/enjoy-digital/litex.git synced 2025-01-04 09:52:26 -05:00
Code Issues Projects Releases Packages Wiki Activity
3943 commits 42 branches 14 tags 31 MiB
Commit graph

3943 commits

This branch
This branch
All branches
Author SHA1 Message Date
Florent Kermarrec
468780c045 soc/cores/spi_flash: add endianness parameter 2018-10-30 10:19:21 +01:00
Florent Kermarrec
6f3131e259 soc/interconnect/stream_packet: use reverse_bytes from litex.gen 2018-10-30 10:16:55 +01:00
Florent Kermarrec
b796853893 gen: add common with reverse_bits/reverse_bytes functions 2018-10-30 10:15:29 +01:00
Florent Kermarrec
71fc34d7b6 boards/targets/ulx3s: reduce l2_size 2018-10-30 10:14:48 +01:00
Florent Kermarrec
75d073f394 build/lattice/prjtrellis: fix typo 2018-10-30 10:14:30 +01:00
Florent Kermarrec
6048a5291c build/lattice/prjtrellis: modify generated verilog instead of creating a wrapper, handle inouts. 
nextpnr expects TRELLIS_IO on all ios, it's not possible to ensure that with a wrapper.
We now just modify the generated verilog to insert the io constraints and TRELLIS_IOs.
 2018-10-30 08:54:30 +01:00
Florent Kermarrec
2243f628f7 build/lattice/common: fix LatticeECPXPrjTrellisTristateImpl 2018-10-30 08:47:12 +01:00
Tim Ansell
3a8bb94ab4
Merge pull request #121 from cr1901/patch-3 
Update vivado.py
 2018-10-29 20:54:23 -07:00
William D. Jones
f3111e1142
Update vivado.py 
Fix regression which caused Vivado to not be run at all.
 2018-10-29 23:43:32 -04:00
Florent Kermarrec
98fa899692 boards/targets: add ulx3s 2018-10-29 19:24:28 +01:00
Florent Kermarrec
7d779473f1 boards/platforms: add ulx3s 2018-10-29 19:23:59 +01:00
Florent Kermarrec
d9dcad33a4 build/lattice/prjtrellis: add inout support 2018-10-29 19:23:21 +01:00
Florent Kermarrec
091ad799b0 build/lattice/common: add tristate support 2018-10-29 19:22:04 +01:00
Florent Kermarrec
23acefb14e boards/targets/versaecp55g_prjtrellis: simple.py example working, specific target no longer needed 
simple.py configuration tested:
python3 simple.py --cpu-type=lm32 --gateware-toolchain=prjtrellis litex.boards.platforms.versaecp55g
python3 simple.py --cpu-type=vexriscv --gateware-toolchain=prjtrellis litex.boards.platforms.versaecp55g
 2018-10-29 16:02:25 +01:00
Florent Kermarrec
1097f82283 build/lattice/prjtrellis: set default toolchain_path to "/opt/prjtrellis" 2018-10-29 15:58:54 +01:00
Florent Kermarrec
52917a710e boards/targets/simple: add gateware-toolchain parameter 2018-10-29 15:56:46 +01:00
Florent Kermarrec
d84083f642 boards/platforms/versaecp55g: use ftdi serial pins 2018-10-29 15:39:51 +01:00
Florent Kermarrec
c05b9ef2ad build/lattice/prjtrellis: test and fix iowrapper multi-bit signals support 2018-10-29 13:26:29 +01:00
Florent Kermarrec
a8f819fec2 Merge branch 'master' of http://github.com/enjoy-digital/litex 2018-10-29 11:48:10 +01:00
Florent Kermarrec
4eb314a252 boards/targets/versaecp55g: use new iowrapper support, basic led blink and ios working :) 2018-10-29 11:46:03 +01:00
Florent Kermarrec
27ec2a59e2 build/lattice/prjtrellis: generate iowrapper to set constraints and TRELLIS_IO 
PrjTrellis does not yet have constraint files support, constraints are set
with signal attributes and specific TRELLIS_IO instances are requested. This
iowrapper does this work for us automatically.

Remove this code and replace with a constraint file generation code when
PrjTrellis will have constraint file support.
 2018-10-29 11:44:31 +01:00
Florent Kermarrec
c506c9752c gen/fhdl/verilog: set direction to io signals 2018-10-29 11:41:04 +01:00
Tim Ansell
9815920946
Merge pull request #120 from mithro/master 
litex/build: Always run Vivado.
 2018-10-29 02:08:20 -07:00
Tim 'mithro' Ansell
1cac079efa litex/build: Always run Vivado. 
When using Yosys for synthesis, still need Vivado for place and route.
 2018-10-29 02:04:44 -07:00
Florent Kermarrec
49dab3b448 build/lattice/prjtrellis: simplify code, remove some workarounds 2018-10-29 09:40:35 +01:00
Florent Kermarrec
a73d9d96b1 build/xilinx/vivado: fix merge issue 2018-10-29 08:26:13 +01:00
Florent Kermarrec
3e189379f9 boards/targets: add versa ecp55g prjtrellis target (experimental) 2018-10-28 19:34:17 +01:00
Florent Kermarrec
a69197d2db build/lattice: add initial prjtrellis support 2018-10-28 17:51:16 +01:00
Florent Kermarrec
397e3c7682 build/lattice/diamond: use bash on linux 2018-10-28 15:40:52 +01:00
Florent Kermarrec
d029cd243d build/lattice: improve special_overrides names (vendor_family) 2018-10-28 15:40:10 +01:00
enjoy-digital
60665358d4
Merge pull request #114 from mithro/xilinx+yosys 
WIP: Allow Yosys to be used for synthesis with Vivado
 2018-10-28 15:00:06 +01:00
enjoy-digital
b200ce9983
Merge branch 'master' into xilinx+yosys 2018-10-28 14:59:03 +01:00
enjoy-digital
8c0982a1d5
Merge pull request #118 from mithro/uart-sync 
uart: Enable buffering the FIFO.
 2018-10-28 08:02:22 +01:00
Tim 'mithro' Ansell
ba0dd5728e uart: Enable buffering the FIFO. 
On the iCE40 FPGA, adding buffering allows the SyncFIFO to be placed in
block RAM rather than consuming a large amount of resources.
 2018-10-27 16:04:58 -07:00
Florent Kermarrec
f916705313 README: improve instructions for litex_sim 2018-10-27 11:06:53 +02:00
Florent Kermarrec
e3935b481e build/sim/verilator: don't use THEADS parameters when threads=1 
Allow using old (non multi-threaded) version of Verilator
 2018-10-27 11:06:34 +02:00
Florent Kermarrec
a44181e716 soc_sdram: update litedram 2018-10-19 18:37:55 +02:00
Florent Kermarrec
ab6a530a24 bios/sdram: s7ddrphy now has bitslip in fabric, show scan for each module/bitslip and remove silent mode 2018-10-18 13:42:51 +02:00
Florent Kermarrec
b8be9545cc build/xilinx/vivado: enable xpm libraries 2018-10-18 09:25:34 +02:00
Florent Kermarrec
ab8cf3e345 soc/cores/clock: add margin parameter to create_clkout (default = 1%) 2018-10-16 14:57:37 +02:00
Florent Kermarrec
915c2f417a bios/sdram: improve write/read leveling 
write_leveling: select last 0 to 1 transition.
read_leveling: do it by module (select best bitslip for each module)
 2018-10-10 10:42:56 +02:00
Florent Kermarrec
deffa60324 platforms/kc705: add ddram_dual_rank 2018-10-09 15:39:03 +02:00
Florent Kermarrec
10624c26da bios/main: handle all types of carriage return (\r, \n, \r\n or \n\r) 2018-10-09 10:06:51 +02:00
enjoy-digital
9f083e9bd3
Merge pull request #116 from stffrdhrn/sim-uart 
sim: serial: Send '\r\n' instead of just '\n'
 2018-10-09 07:32:31 +02:00
Stafford Horne
8877dba7e9 sim: serial: Send '\r\n' instead of just '\n' 
This fixes an issue when running with the HDMI2USB firmware which
expects \r\n to come from the UART.  Since the verilator adapter
is just sending \n commands cannot be executed.

Also, one minor whitespace cleanup. (could remove if needed)
 2018-10-09 11:18:11 +09:00
Florent Kermarrec
d187921500 cpu_interface: fix select_triple when only one specified 2018-10-08 17:01:04 +02:00
Florent Kermarrec
3b27d2ae89 soc/integration/cpu_interface: generate error if unable to find any of the cross compilation toolchains 2018-10-06 21:32:38 +02:00
Florent Kermarrec
168b07b9a2 soc_core: add csr range check 2018-10-06 20:55:16 +02:00
Tim 'mithro' Ansell
ace976242e build.xilinx: Convert attributes to something Yosys understands. 
Convert keep, dont_touch and async_reg to something Yosys understands.

Write out an EDIF file with the attributes so that Vivado can use them.
(Requires Yosys with commit
115ca57647)
 2018-10-05 12:48:30 -07:00
enjoy-digital
6febb6826c
Merge pull request #112 from cr1901/8k-b-evn 
build/platforms: Add ice40_hx8k_b_evn from Migen.
 2018-10-04 21:12:33 +02:00