Sebastien Bourdeauducq
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48b6733c33
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cores/gpio: fix import
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2015-09-29 18:13:59 +08:00 |
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Sebastien Bourdeauducq
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dd7dfb0d5e
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soc_core: simplify settings (assume CPU and CSR present)
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2015-09-29 10:19:42 +08:00 |
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Sebastien Bourdeauducq
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b1a90053f5
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minor fixes
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2015-09-29 10:19:00 +08:00 |
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Sebastien Bourdeauducq
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523377efbe
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basic out-of-tree build support (OK on PPro)
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2015-09-28 20:33:37 +08:00 |
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Sebastien Bourdeauducq
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e92d00f767
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move software into misoc
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2015-09-28 15:30:19 +08:00 |
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Sebastien Bourdeauducq
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27b2383607
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sdram working on PPro
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2015-09-26 21:51:22 +08:00 |
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Sebastien Bourdeauducq
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67133f3542
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replace flen with len
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2015-09-26 18:50:11 +08:00 |
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Sebastien Bourdeauducq
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da425d1bcb
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add stream, fix CPUs and more imports. simple target boots on ppro.
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2015-09-26 16:44:21 +08:00 |
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Sebastien Bourdeauducq
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75ef2f9004
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fix most imports
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2015-09-25 18:43:20 +08:00 |
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Sebastien Bourdeauducq
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f69674e89c
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interconnect: add bus/bank components from Migen
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2015-09-24 20:48:18 +08:00 |
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Sebastien Bourdeauducq
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ecdc4101b4
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lasmicon: enable refresh at all times
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2015-09-24 16:01:08 +08:00 |
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Sebastien Bourdeauducq
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9b08b037e4
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break down sdram, improve consistency of core names
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2015-09-24 15:59:55 +08:00 |
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Sebastien Bourdeauducq
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0f410e45f1
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cores directory
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2015-09-24 09:05:10 +08:00 |
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Sebastien Bourdeauducq
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83509163df
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reorganization WIP: flatten core structure (SDRAM still needs to be done)
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2015-09-24 00:18:27 +08:00 |
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Sebastien Bourdeauducq
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82236d9b40
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migen.fhdl.std -> migen
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2015-09-23 00:36:47 +08:00 |
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Sebastien Bourdeauducq
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bd74d39338
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misoclib -> misoc
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2015-09-23 00:35:02 +08:00 |