108 Commits

Author	SHA1	Message	Date
Sebastien Bourdeauducq	badba89686	fhdl: support nested statement lists	2013-01-05 14:18:15 +01:00
Sebastien Bourdeauducq	70e97e0456	Fix various errors from new bitwidth/signedness system conversion	2012-11-29 23:36:55 +01:00
Sebastien Bourdeauducq	261166d92b	fhdl/verilog: make signal behave as integers in arithmetic (MyHDL style) ... See http://jandecaluwe.com/hdldesign/counting.html	2012-11-29 22:59:54 +01:00
Sebastien Bourdeauducq	50ed73c937	New specification for width and signedness	2012-11-29 21:22:38 +01:00
Sebastien Bourdeauducq	6eebfce44a	Refactor Case	2012-11-29 01:11:15 +01:00
Sebastien Bourdeauducq	fee22a4631	Remove Constant	2012-11-28 23:18:43 +01:00
Sebastien Bourdeauducq	9d3e218863	fhdl: use object creation counter (HUID) as hash. This finally makes the generated code textually the same across runs.	2012-11-23 18:38:03 +01:00
Sebastien Bourdeauducq	51e2e6ecd0	fhdl/verilog: remove empty cases	2012-11-18 16:32:51 +01:00
Sebastien Bourdeauducq	c273866b08	fhdl: support expressions in instance ports	2012-09-22 20:51:10 +02:00
Sebastien Bourdeauducq	2fc9cae88a	fhdl: support inverted clock ports in instances	2012-09-22 20:50:49 +02:00
Sebastien Bourdeauducq	2e14569b5c	fhdl/verilog: sort clock domains by name	2012-09-11 10:00:03 +02:00
Sebastien Bourdeauducq	9a18a9df3f	fhdl: list signals in execution order	2012-09-11 09:59:37 +02:00
Sebastien Bourdeauducq	e16353a281	Multi-clock design support + new instance API	2012-09-10 23:45:02 +02:00
Sebastien Bourdeauducq	8de192dfbd	x.bv.width -> len(x)	2012-07-13 18:32:54 +02:00
Sebastien Bourdeauducq	7f47a2568a	fhdl: remove _StatementList	2012-07-13 17:07:56 +02:00
Sebastien Bourdeauducq	ed27783a53	fhdl: arrays (TODO: use correct BV for intermediate signals)	2012-07-09 15:16:38 +02:00
Sebastien Bourdeauducq	398ece8fe2	fhdl/verilog: add option to display which comb blocks are run ... This is a debug hack to help find combinatorial loops in designs.	2012-04-30 16:38:40 -05:00
Sebastien Bourdeauducq	2a4e49e381	fhdl: phase out pads	2012-04-02 19:21:43 +02:00
Sebastien Bourdeauducq	623e8e436a	fhdl/verilog: do not attempt to initialize instance and mem output signals	2012-04-02 12:59:42 +02:00
Sebastien Bourdeauducq	f3ae22f488	fhdl/verilog: initialize internal read-only signals with their reset values	2012-04-01 16:39:11 +02:00
Sebastien Bourdeauducq	90184b22d2	fhdl/verilog: fix signed constant conversion	2012-03-06 16:45:44 +01:00
Sebastien Bourdeauducq	a1ad30faab	fhdl/verilog: properly connect instance inouts	2012-02-17 11:08:41 +01:00
Sebastien Bourdeauducq	ca7056b07f	fhdl: support forwarding of bidirectional signals from instance ports	2012-02-16 18:34:32 +01:00
Sebastien Bourdeauducq	1eb348c573	fhdl: do not attempt slicing non-array signals to keep Verilog happy	2012-02-06 18:07:02 +01:00
Sebastien Bourdeauducq	5405a83ff9	fhdl: memories working	2012-01-27 20:22:17 +01:00
Sebastien Bourdeauducq	a5bd111370	fhdl/verilog: clean up signal classification and support memory descriptions	2012-01-27 16:54:48 +01:00
Sebastien Bourdeauducq	d3d5b481fe	Include fragment pads in pre-naming dictionary	2012-01-20 22:59:40 +01:00
Sebastien Bourdeauducq	e9be3241f6	Fix instance support	2012-01-20 22:36:17 +01:00
Sebastien Bourdeauducq	e4f531a739	Include unused I/Os in pre-naming dictionary and register signals with name_override	2012-01-20 22:20:32 +01:00
Sebastien Bourdeauducq	4eac60d181	New naming system: second attempt	2012-01-19 18:25:25 +01:00
Sebastien Bourdeauducq	bdde97f5fd	New naming system beginning to work	2012-01-16 18:42:55 +01:00
Sebastien Bourdeauducq	ab8e08a2ed	fhdl: new naming system (broken)	2012-01-16 18:09:52 +01:00
Sebastien Bourdeauducq	aa8b8da684	fhdl: allow None statements	2012-01-15 17:45:54 +01:00
Sebastien Bourdeauducq	7b395b565e	verilog: split comb block, use assign statements	2012-01-07 12:19:06 +01:00
Sebastien Bourdeauducq	f209bf6b33	convtools -> tools	2012-01-07 00:39:28 +01:00
Sebastien Bourdeauducq	9366a226bb	Convert -> convert	2012-01-05 19:27:33 +01:00
Sebastien Bourdeauducq	8a394f9159	verilog: comb reset	2011-12-22 00:04:53 +01:00
Sebastien Bourdeauducq	4d6be55e9f	verilog: break down Convert function	2011-12-21 23:08:50 +01:00
Sebastien Bourdeauducq	26e0b817e8	verilog: ignore variable property in combinatorial block	2011-12-21 23:00:36 +01:00
Sebastien Bourdeauducq	7456195775	Consistent names	2011-12-21 22:57:07 +01:00
Sebastien Bourdeauducq	6f8a6db40a	verilog: get the simulator to run the combinatorial process at the beginning	2011-12-17 15:20:22 +01:00
Sebastien Bourdeauducq	ec47394012	verilog: support for float parameters in instances	2011-12-17 14:59:27 +01:00
Sebastien Bourdeauducq	ee6ca729a2	verilog: user-definable reset and clock	2011-12-16 22:25:05 +01:00
Sebastien Bourdeauducq	c7b9dfc203	fhdl: simpler syntax	2011-12-16 21:30:14 +01:00
Sebastien Bourdeauducq	39b7190334	Pay a bit more attention to PEP8	2011-12-16 16:02:55 +01:00
Sebastien Bourdeauducq	c840848dba	verilog: use blocking assignment in combinatorial process	2011-12-13 14:09:12 +01:00
Sebastien Bourdeauducq	a72faaecdd	fhdl: allow a namespace to be specified for Verilog conversion	2011-12-13 00:24:40 +01:00
Sebastien Bourdeauducq	eee6980a36	fhdl: support Constant parameters for Verilog conversion	2011-12-11 20:17:51 +01:00
Sebastien Bourdeauducq	a49ecc4331	fhdl: pad support in fragments	2011-12-10 20:25:24 +01:00
Sebastien Bourdeauducq	fa63cc1ec8	fhdl: replication support	2011-12-09 13:11:34 +01:00
Sebastien Bourdeauducq	b0c5b74c22	verilog: handle default in case statements	2011-12-08 23:04:20 +01:00
Sebastien Bourdeauducq	bf021efa2b	verilog: fix unary operator conversion	2011-12-08 21:15:24 +01:00
Sebastien Bourdeauducq	1b637cea61	Instance support	2011-12-08 16:35:32 +01:00
Sebastien Bourdeauducq	0e8d894a35	Variable conversion	2011-12-05 22:00:06 +01:00
Sebastien Bourdeauducq	4340680704	Cleanup	2011-12-05 19:25:32 +01:00
Sebastien Bourdeauducq	ec51f09c98	Case support + register bank generator	2011-12-05 17:43:56 +01:00
Sebastien Bourdeauducq	e099f4d52f	Reset insertion	2011-12-04 22:41:50 +01:00
Sebastien Bourdeauducq	cd8544c758	Verilog generator	2011-12-04 22:26:32 +01:00