Florent Kermarrec
4ba3ad5409
sim/gtkwave: Update/fix SignalNamespace import (And make it public in fhdl/namer).
2023-11-09 10:29:43 +01:00
Florent Kermarrec
4610713797
gen/fhdl/verilog: Ensure top is not None to build hierarchy.
2023-11-08 16:58:23 +01:00
Florent Kermarrec
657252c573
gen/fhdl/namer: Update copyrights.
2023-11-06 17:55:54 +01:00
Florent Kermarrec
5b989bcb0e
gen/fhdl/verilog: Switch Assign/Operator types to IntEnum.
2023-11-06 17:24:03 +01:00
Florent Kermarrec
ef4235a5d9
gen/fhdl/namer: Use _ for private functions and remove build_namespace.
2023-11-06 16:21:33 +01:00
Florent Kermarrec
af508fddc5
gen/fhdl/namer: Improve/Simplify SignalNamespace.get_name method.
2023-11-06 15:54:19 +01:00
Florent Kermarrec
9ce29224a1
gen/fhdl/namer: Add all_numbers to HierarchyNode to avoid hasattr use.
2023-11-06 15:36:08 +01:00
Florent Kermarrec
3df23a27f5
gen/fhdl/namer: Avoid deep level of nesting on build_signal_name_dict_for_group.
2023-11-06 13:56:25 +01:00
Florent Kermarrec
c8a96b8d79
gen/fhdl/namer: Add update method to HierarchyNode to replace update_hierarchy_node.
2023-11-06 13:52:02 +01:00
Florent Kermarrec
c0057672d6
gen/fhdl/namer: Split build_signal_name_dict with build_hierarchical_name and update_name_dict_with_group.
2023-11-06 13:43:14 +01:00
Florent Kermarrec
0efccae8b4
gen/fhdl/namer: Simplify/Remove some redundancies.
2023-11-06 13:34:23 +01:00
Florent Kermarrec
16804acaa8
gen/fhdl/namer: Add update_hierarchy_node function to reduce build_hierarchy_tree complexity.
2023-11-06 13:19:19 +01:00
Florent Kermarrec
19a3ab2614
gen/fhdl/namer: Improve class/variable names.
2023-11-06 12:51:37 +01:00
Florent Kermarrec
9548259a5c
gen/fhdl/namer: Simplify build_namespace and add comments.
2023-11-06 12:31:48 +01:00
Florent Kermarrec
a65d471ed2
gen/fhdl/namer: Simplify _invert_pnd_build_signal_groups/_build_pnd and add comments.
2023-11-06 11:58:29 +01:00
Florent Kermarrec
36e47052b2
gen/fhdl/namer: Simplify _invert_pnd/_list_conflicting_signals/_set_use_number/_build_pnd_for_group and add comments.
2023-11-06 11:49:48 +01:00
Florent Kermarrec
d28b7a1172
gen/fhdl/namer: Simplify _set_use_name/_build_pnd_from_tree and add comments.
2023-11-06 11:32:52 +01:00
Florent Kermarrec
6214aa69af
gen/fhdl/namer: Simplify _build_tree and add comments.
2023-11-06 10:52:44 +01:00
Florent Kermarrec
1e805a8789
fhdl/namer: Remove debug and add docstring comments.
2023-11-06 09:38:17 +01:00
Florent Kermarrec
6f431fa2b1
gen/fhdl: Cleanup/Simplify hierarchy generation.
2023-11-03 14:57:48 +01:00
Florent Kermarrec
a1704a045e
gen/fhdl/instance: Ident Parameters/IOs on max length of names.
2023-11-03 12:31:14 +01:00
Florent Kermarrec
4627e8958f
gen/fhdl/instance: Generate Parameters/Inputs/Outputs/InOuts separators and generate IOs in Input/Output/InOut order.
2023-11-03 12:11:53 +01:00
Florent Kermarrec
18c0541e6a
gen/fhdl/instance: Add instance description.
2023-11-03 11:53:32 +01:00
Florent Kermarrec
079a0a7b75
gen/fhdl/instance: First cleanup pass.
2023-11-03 11:47:07 +01:00
Florent Kermarrec
dee64b346f
gen/fhdl: Integrate Migen's Instance verilog generation to be able to customize it to our needs.
2023-11-03 11:40:16 +01:00
Florent Kermarrec
fe19ee464e
gen/fhdl/memory: Rename memory_emit_verilog to _memory_generate_verilog.
2023-11-03 11:29:48 +01:00
Florent Kermarrec
e6d950bcb0
gen/fhdl/verilog: Add module hierarchy generation after module definition.
...
Will give a better overview of the generated verilog and will also ease comparing changes/track regressions.
2023-11-03 11:08:40 +01:00
Florent Kermarrec
4a1486b1db
gen/fhdl/hierarchy: Add with_colors parameters to allow enabling/disabling colors.
2023-11-03 11:06:41 +01:00
Florent Kermarrec
4497569118
gen/context: Rename soc to top.
2023-11-03 11:05:57 +01:00
Florent Kermarrec
27c55999c6
gen/common/colorer: Add enable parameter to allow enabling/disabling coloring.
2023-11-03 11:05:09 +01:00
Florent Kermarrec
b60bd92533
gen/fhdl/verilog: Rename _print_xy to _generate_xy and cleanup imports.
2023-11-03 10:14:38 +01:00
Florent Kermarrec
856d7452b3
gen/fhdl/module: Ensure Module/Special/ClockDomains are initialized before adding them as submodules/specials/clock_domains.
2023-10-27 12:26:54 +02:00
Marcus Comstedt
6da1482336
gen/fhdl/verilog: Fix #1777 .
2023-09-14 17:53:51 +02:00
Florent Kermarrec
8f54386aab
gen/fhdl/module: Add some comments.
2023-08-24 09:17:35 +02:00
Florent Kermarrec
bf79c9032a
gen/genlib/misc/WaitTimer: Cast t to int and minor cosmetic cleanup.
2023-07-31 11:27:47 +02:00
Florent Kermarrec
ed12f8787d
litex/gen: Add some comments.
2023-07-27 16:18:30 +02:00
Florent Kermarrec
095cfb7811
litex/gen: Split common in common/context/reduce/signal.
2023-07-27 15:02:37 +02:00
Florent Kermarrec
72a1592bee
litex/gen: Add initial/minimal LiteXContext to easily get build context from modules.
...
Still a PoC and need to think a bit more about it, but will allow fixing AsyncFIFO issue
on Efinix FPGAs.
2023-07-27 13:27:15 +02:00
Florent Kermarrec
6e46710678
gen/fhdl/module: Fix CSR clock domain renaming to cores converted to LiteXModule, thanks @smunaut.
2023-07-14 10:01:32 +02:00
Florent Kermarrec
d18c6316f4
gen/fhdl/verilog: Improve signal sort by name instead of duid to improve reproducibility.
2023-07-10 11:24:46 +02:00
Florent Kermarrec
e62f51c3eb
gen/genlib/cdc: Add missing import.
2023-07-07 11:51:04 +02:00
Florent Kermarrec
2b941cdcd9
gen/genlib: Add copy of genlib.cdc modules that we are using and not supported by Amaranth to prepare #1727 .
2023-07-06 22:23:54 +02:00
Florent Kermarrec
6f98053b1a
litex/gen: Add copy of genlib.misc to prepare for #1727 .
2023-07-06 22:03:41 +02:00
Florent Kermarrec
9c890a0a27
gen/fhdl/verilog: Simplify/Rename registers initialization parameter.
2023-05-17 17:24:06 +02:00
bunnie
4e15fd54b0
add an option to generate without reg initializers (asic targets)
...
ASIC targets can't set a reg to a known value on boot, so for
more accurate simulations it would be nice to have an option
in the platform to specify generating the verilog without 'reg'
initializers. The presence of these initializers can mask
problems in simulations with X-prop that can lead to missing
explicit reset conditions.
2023-05-15 18:45:10 +08:00
Florent Kermarrec
2f5481dbb9
gen/common: Add Unsigned/Signed Signal wrappers.
2023-02-28 10:17:16 +01:00
Florent Kermarrec
c1ee154340
global: Move Open definition to gen/common and use it.
2023-02-21 09:10:15 +01:00
Florent Kermarrec
653b74fe98
gen/fhdl/module: Fix typo.
2023-02-21 08:26:21 +01:00
Florent Kermarrec
fac9fb81a2
gen/fhdl/module: Add add/get_module methods to simplify user design and avoid direct use of setattr/getattr.
2022-12-08 14:20:38 +01:00
Florent Kermarrec
240b24b7ff
gen/fhdl/hierarchy: Use [] for BlackBoxes.
2022-11-08 15:08:12 +01:00
