Florent Kermarrec
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0db6e1d624
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soc/cpuif: fix get_csr_header when obj is Memory (thanks ccube)
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2015-04-03 11:14:28 +02:00 |
Sebastien Bourdeauducq
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875abdeb8d
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make.py: use os.path.join
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2015-04-03 16:00:07 +08:00 |
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Sebastien Bourdeauducq
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73d3b8487c
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crt0-or1k: clean up indentation
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2015-04-03 13:23:28 +08:00 |
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Sebastien Bourdeauducq
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357c807eb1
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Merge branch 'master' of github.com:m-labs/migen
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2015-04-02 20:23:12 +08:00 |
Yann Sionneau
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ce429841d5
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kc705: fix typo in platform file (LPC definition)
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2015-04-02 20:21:20 +08:00 |
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Florent Kermarrec
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b437dc3185
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remove use of _r prefix on CSRs
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2015-04-02 12:18:43 +02:00 |
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Florent Kermarrec
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ce0ff1e341
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remove use of _r prefix on CSRs
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2015-04-02 12:15:56 +02:00 |
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Florent Kermarrec
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d67f24ddc7
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migen/bank/description: remove support of _r prefix in CSRs
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2015-04-02 12:13:22 +02:00 |
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Sebastien Bourdeauducq
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696819cc7f
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move gpio from cpu.peripherals to com
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2015-04-02 17:17:33 +08:00 |
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Sebastien Bourdeauducq
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63f14f3f30
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libbase: implement flush_l2_cache for or1k
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2015-04-02 16:47:03 +08:00 |
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Sebastien Bourdeauducq
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382ed013af
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minor cleanups
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2015-04-02 14:40:29 +08:00 |
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Sebastien Bourdeauducq
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bbdbf87599
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Merge branch 'master' of github.com:m-labs/misoc
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2015-04-02 10:14:24 +08:00 |
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Florent Kermarrec
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60124be293
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adapt LiteSATA to new SoC
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2015-04-01 22:52:19 +02:00 |
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Florent Kermarrec
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dcdf5df4de
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adapt LiteEth to new SoC
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2015-04-01 22:50:29 +02:00 |
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Florent Kermarrec
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f65c0a3c95
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adapt LiteScope to new SoC
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2015-04-01 22:46:24 +02:00 |
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Florent Kermarrec
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2d23ab7a85
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soc/sdram: fix do_finalize
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2015-04-01 22:38:04 +02:00 |
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Sebastien Bourdeauducq
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2900429e65
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soc: use set
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2015-04-02 00:14:56 +08:00 |
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Sebastien Bourdeauducq
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369086a178
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soc: simplify integrated memory parameters
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2015-04-02 00:09:38 +08:00 |
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Sebastien Bourdeauducq
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273242b399
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soc/sdram: minor cleanup
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2015-04-01 23:41:55 +08:00 |
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Sebastien Bourdeauducq
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6e2a662dd7
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litesata: adapt to new SoC API
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2015-04-01 17:37:53 +08:00 |
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Sebastien Bourdeauducq
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9599eb6fae
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soc: remove cpu_boot_file argument
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2015-04-01 17:32:45 +08:00 |
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Sebastien Bourdeauducq
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fb86445d14
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soc: remove cpu_or_bridge and with_cpu arguments
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2015-04-01 17:29:51 +08:00 |
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Sebastien Bourdeauducq
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a148af97ba
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soc: retrieve csr and memory regions using methods
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2015-04-01 16:49:32 +08:00 |
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Sebastien Bourdeauducq
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8b19a11cd7
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soc: use add_wb_master function
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2015-04-01 15:56:54 +08:00 |
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Sebastien Bourdeauducq
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2a1112b912
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soc: simplify/fix csr busword
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2015-04-01 15:48:56 +08:00 |
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Sebastien Bourdeauducq
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04f29e97e2
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soc: remove unnecessary imports
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2015-04-01 15:15:09 +08:00 |
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Sebastien Bourdeauducq
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5113301130
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soc: improve memory region conflict check
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2015-04-01 15:14:02 +08:00 |
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Sebastien Bourdeauducq
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980791e2b8
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soc: remove ns function
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2015-04-01 14:33:12 +08:00 |
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Florent Kermarrec
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e5ddd1263c
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remove redundant xilinx_strace_tailor.sh
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2015-03-30 18:58:34 +02:00 |
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Sebastien Bourdeauducq
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b469571afe
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move xilinx_strace_tailor to tools
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2015-03-30 19:42:11 +08:00 |
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Sebastien Bourdeauducq
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c169f0b189
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Revert "migen: create VerilogConvert and EDIFConvert classes and return it with convert functions"
This reverts commit f03aa76292.
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2015-03-30 19:41:16 +08:00 |
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Sebastien Bourdeauducq
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dc88295338
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Revert "migen/fhdl: pass fdict filename --> contents to specials"
This reverts commit ea04947519.
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2015-03-30 19:41:13 +08:00 |
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Sebastien Bourdeauducq
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b1c811a3d1
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Revert "migen/fhdl/specials: use fdict to pass memory initialization files to VerilogConvert and print them in __str__ method"
This reverts commit 95cfc444e6.
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2015-03-30 19:41:04 +08:00 |
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Florent Kermarrec
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15e24b6c10
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mibuild/platforms: fix minispartan6
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2015-03-30 11:42:14 +02:00 |
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Florent Kermarrec
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95cfc444e6
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migen/fhdl/specials: use fdict to pass memory initialization files to VerilogConvert and print them in __str__ method
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2015-03-30 11:37:59 +02:00 |
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Florent Kermarrec
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ea04947519
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migen/fhdl: pass fdict filename --> contents to specials
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2015-03-30 11:37:57 +02:00 |
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Florent Kermarrec
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f03aa76292
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migen: create VerilogConvert and EDIFConvert classes and return it with convert functions
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2015-03-30 11:37:55 +02:00 |
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Sebastien Bourdeauducq
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21c5fb6f6c
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Merge branch 'master' of github.com:m-labs/migen
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2015-03-30 00:52:15 +08:00 |
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Sebastien Bourdeauducq
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19a6157478
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platforms/lx9_microboard,usrp_b100: fix bitgen opts
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2015-03-30 00:44:56 +08:00 |
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Florent Kermarrec
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263fc47728
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platforms/kc705: fix .bin generation with ISE and Vivado
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2015-03-29 21:15:20 +08:00 |
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Florent Kermarrec
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b313772a0c
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sdram: remove redundant with_l2 parameter (equivalent to l2_size != 0)
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2015-03-29 12:34:40 +02:00 |
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Florent Kermarrec
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17f3590a7c
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platforms/kc705: add iMPACT programmer
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2015-03-29 12:15:39 +02:00 |
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Florent Kermarrec
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be20fbabe4
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soc: limit main_ram_size to 256MB (we should modify mem_map to allow larger memories, this was the probably ARTIQ runtime issue....!!)
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2015-03-28 23:35:44 +01:00 |
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Florent Kermarrec
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0649ded5fd
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soc: simplify main_ram_size computation and share it between LASMIcon and Minicon
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2015-03-28 23:10:33 +01:00 |
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Florent Kermarrec
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a8d91c0c1d
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sdram/module: fix MT8JTF12864, rowbits is 14 and not 16.... (16 was used from the beginning, but it does not fix the runtime issue)
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2015-03-28 16:35:15 +01:00 |
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Florent Kermarrec
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75ee8a5db9
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sdram/phy/simphy: OK with DDR3
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2015-03-28 01:59:55 +01:00 |
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Florent Kermarrec
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51ce7cad6f
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sdram/phy/simphy: expose settings to user and test with DDR/LPDDR/DDR2
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2015-03-28 01:18:35 +01:00 |
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Florent Kermarrec
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a95b3f8f13
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sdram/core/lasmicon: add enabled parameter to refresher (for some simulations we need to disable it)
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2015-03-28 01:17:50 +01:00 |
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Florent Kermarrec
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7fe748e1b0
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sdram/module: clean up tREFI. (use 64ms/8k or 4k)
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2015-03-28 01:09:21 +01:00 |
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Sebastien Bourdeauducq
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54a88da5b8
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Merge branch 'master' of https://github.com/m-labs/misoc
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2015-03-27 19:22:29 +01:00 |