Sebastien Bourdeauducq
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1897b74f97
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genlib/record: add eq
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2013-03-24 00:50:33 +01:00 |
|
Sebastien Bourdeauducq
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6010308317
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software/videomixer: report char position + detected resolution, detect phase at beginning
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2013-03-24 00:46:23 +01:00 |
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Sebastien Bourdeauducq
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1333367de8
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dvisampler: add resolution detection
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2013-03-24 00:45:29 +01:00 |
|
Sebastien Bourdeauducq
|
ee5bfd4d3d
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dvisampler/charsync: report position
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2013-03-24 00:44:50 +01:00 |
|
Sebastien Bourdeauducq
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99f9ffa7e8
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dvisampler/decoding: set C to 0 during data
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2013-03-24 00:44:19 +01:00 |
|
Sebastien Bourdeauducq
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fb9a2788e8
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dvisampler/charsync: fix found_control signal
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2013-03-24 00:43:22 +01:00 |
|
Sebastien Bourdeauducq
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80f3e97ca9
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software/stddef.h: c++ compat for NULL
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2013-03-24 00:17:42 +01:00 |
Florent Kermarrec
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492a5acfe3
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add Run Length Encoding
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2013-03-23 22:06:08 +01:00 |
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Sebastien Bourdeauducq
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003f1950cd
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xilinx_ise: fix clock domain names
|
2013-03-23 19:37:16 +01:00 |
|
Sebastien Bourdeauducq
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e06585d9fe
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dvisampler: clean up EDID data
|
2013-03-23 13:48:40 +01:00 |
|
Florent Kermarrec
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eeab7051be
|
remove doc (to be re-written)
|
2013-03-23 12:28:18 +01:00 |
|
Florent Kermarrec
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88748bd74f
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simplify recorder
|
2013-03-23 12:26:22 +01:00 |
|
Sebastien Bourdeauducq
|
34b8388b45
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dvisampler: decode before channel sync
|
2013-03-22 23:49:25 +01:00 |
|
Sebastien Bourdeauducq
|
037625886d
|
dvisampler: decoding
|
2013-03-22 21:28:17 +01:00 |
|
Sebastien Bourdeauducq
|
d65941d6cc
|
dvisampler: channel synchronization
|
2013-03-22 18:37:10 +01:00 |
|
Sebastien Bourdeauducq
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9d7c679b8c
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genlib/fifo: simple synchronous FIFO
|
2013-03-22 18:18:38 +01:00 |
|
Sebastien Bourdeauducq
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ca431fc7c2
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fhdl/module: support clock domain remapping of submodules
|
2013-03-22 18:17:54 +01:00 |
|
Florent Kermarrec
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99a78b8e33
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clean up
|
2013-03-22 14:01:38 +01:00 |
|
Florent Kermarrec
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5e48f9c005
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update driver api
|
2013-03-22 12:35:12 +01:00 |
|
Florent Kermarrec
|
b1cbfe2326
|
clean up/fixes
|
2013-03-22 11:31:21 +01:00 |
|
Sebastien Bourdeauducq
|
515cdb2bd8
|
dvisampler: character synchronization
|
2013-03-21 22:56:13 +01:00 |
|
Sebastien Bourdeauducq
|
7c4ca4fd66
|
dvisampler/datacapture: deserialize to 10 bits
|
2013-03-21 19:06:15 +01:00 |
|
Sebastien Bourdeauducq
|
fa2331e084
|
dvisampler/clocking: generate pix reset
|
2013-03-21 19:02:04 +01:00 |
|
Sebastien Bourdeauducq
|
2315544b36
|
software/videomixer: quick hack for phase detection
|
2013-03-21 15:32:26 +01:00 |
|
Florent Kermarrec
|
db1ceccca1
|
fix uart2Csr and update miio example
|
2013-03-21 12:18:04 +01:00 |
|
Sebastien Bourdeauducq
|
a6a3d93059
|
software: add videomixer base files
|
2013-03-21 10:42:31 +01:00 |
|
Sebastien Bourdeauducq
|
bb566c9e7c
|
software/bios: change boot order
|
2013-03-21 10:41:56 +01:00 |
|
Sebastien Bourdeauducq
|
a94bf3b2c5
|
genlib/cdc/MultiReg: output clock domain defaults to sys
|
2013-03-21 10:40:02 +01:00 |
|
Sebastien Bourdeauducq
|
0a14c3714b
|
dvisampler: software controlled phase detector
|
2013-03-21 00:46:29 +01:00 |
|
Sebastien Bourdeauducq
|
b38818eb17
|
examples/sim/fir: convert to new API
|
2013-03-19 11:46:27 +01:00 |
|
Florent Kermarrec
|
24211574ec
|
update de0nano example/ remove de1 (wip)
|
2013-03-18 23:03:52 +01:00 |
|
Florent Kermarrec
|
36f3556028
|
Add uart2csr
|
2013-03-18 21:45:07 +01:00 |
|
Sebastien Bourdeauducq
|
28cb97068c
|
dvisampler/clocking: proper pix5x reset synchronization
|
2013-03-18 20:31:59 +01:00 |
|
Sebastien Bourdeauducq
|
5126f616fb
|
dvisampler: use pix5x as IODELAY clock
|
2013-03-18 19:03:17 +01:00 |
|
Sebastien Bourdeauducq
|
17f2b17654
|
fhdl/verilog: optionally disable clock domain creation
|
2013-03-18 18:45:19 +01:00 |
|
Sebastien Bourdeauducq
|
797411c1a9
|
generic_platform: do not create clock domains during Verilog conversion
|
2013-03-18 18:44:58 +01:00 |
|
Sebastien Bourdeauducq
|
af4eb02551
|
examples/basic/arrays: demonstrate lowering of Array in Instance expression
|
2013-03-18 18:37:23 +01:00 |
|
Sebastien Bourdeauducq
|
7a06e9457c
|
Lowering of Special expressions + support ClockSignal/ResetSignal
|
2013-03-18 18:36:50 +01:00 |
|
Sebastien Bourdeauducq
|
48aae9bee5
|
Use Instance.Input(..., ClockSignal/ResetSignal) instead of Instance.ClockPort/ResetPort
|
2013-03-18 17:44:01 +01:00 |
|
Sebastien Bourdeauducq
|
dc55289323
|
fhdl/tools/_ArrayLowerer: complete support for arrays as targets
|
2013-03-18 14:38:01 +01:00 |
|
Sebastien Bourdeauducq
|
e95d2f4779
|
fhdl/tools/value_bits_sign: support not
|
2013-03-18 09:52:43 +01:00 |
|
Sebastien Bourdeauducq
|
0c0140a8fb
|
m1crg: set CLKIN_PERIOD for vga_clock_gen
|
2013-03-17 20:16:58 +01:00 |
|
Sebastien Bourdeauducq
|
74cc045ee1
|
dvisampler/datacapture: connect IODELAY IOCLK0
|
2013-03-17 17:42:22 +01:00 |
|
Sebastien Bourdeauducq
|
621526fb7d
|
dvisampler/datacapture: fix tap counter reg
|
2013-03-17 17:36:49 +01:00 |
|
Sebastien Bourdeauducq
|
3a0cf278fd
|
dvisampler: fixes
|
2013-03-17 15:41:50 +01:00 |
|
Sebastien Bourdeauducq
|
b6fe3ace05
|
fhdl/structure: style fix
|
2013-03-17 15:33:38 +01:00 |
|
Sébastien Bourdeauducq
|
2a4cc3875c
|
Merge pull request #6 from larsclausen/master
Minor improvements
|
2013-03-17 07:33:14 -07:00 |
|
Sebastien Bourdeauducq
|
9f02ced39e
|
dvisampler: add clocking and phase detector
|
2013-03-17 14:43:10 +01:00 |
|
Sebastien Bourdeauducq
|
4bf3190244
|
MultiReg: remove idomain
|
2013-03-15 19:54:25 +01:00 |
|
Sebastien Bourdeauducq
|
0168f83523
|
MultiReg: remove idomain
|
2013-03-15 19:51:29 +01:00 |