34 commits

Author	SHA1	Message	Date
Kenneth Ryerson	85813b3b58	csr/sram: fix reads on high addresses when word_bits != 0	2013-06-03 21:52:23 +02:00
Kenneth Ryerson	e5e3492afe	csr/sram: fix page_bits computation	2013-06-03 21:51:44 +02:00
Sebastien Bourdeauducq	ebbd5ebcd2	bus/csr/SRAM: better handling of writes to memories larger than the CSR width	2013-05-30 18:45:04 +02:00
Sebastien Bourdeauducq	bac62a32a9	Make memory ports part of specials ... This is needed to handle cases where a single memory has ports in two different modules, and one of these modules is subject to clock domain remapping. The clock domain of the port in that module only must be remapped.	2013-05-28 16:11:34 +02:00
Sebastien Bourdeauducq	70ffe86356	New migen.fhdl.std to simplify imports + len->flen	2013-05-22 17:11:09 +02:00
Sebastien Bourdeauducq	7ada0159fd	bus/csr/SRAM: support init	2013-05-19 20:53:37 +02:00
Sebastien Bourdeauducq	8e11fcf1d0	bus/csr/SRAM: fix Module conversion errors	2013-04-14 13:55:04 +02:00
Sebastien Bourdeauducq	29b468529f	bus: replace simple bus module with new bidirectional Record	2013-04-01 21:54:21 +02:00
Sebastien Bourdeauducq	c4f4143591	New CSR API	2013-03-30 17:28:41 +01:00
Sebastien Bourdeauducq	51bec340ab	sim: remove PureSimulable (superseded by Module)	2013-03-15 19:41:30 +01:00
Sebastien Bourdeauducq	04df076fba	bank: automatic register naming	2013-03-12 15:45:24 +01:00
Sebastien Bourdeauducq	b75fb7f97c	csr/SRAM: support for writes with memory widths larger than bus words	2013-03-09 00:50:57 +01:00
Sebastien Bourdeauducq	9b4ca987e0	bus/csr: support memories with larger word width than the bus (read only)	2013-03-03 19:27:13 +01:00
Sebastien Bourdeauducq	d2491828a4	csr/SRAM: prefix page register with memory name	2013-03-01 12:06:12 +01:00
Sebastien Bourdeauducq	49cfba50fa	New 'specials' API	2013-02-22 17:56:35 +01:00
Sebastien Bourdeauducq	3fae6c8f03	Do not use super()	2012-12-18 14:54:33 +01:00
Sebastien Bourdeauducq	280a87ea69	elsewhere: do not create interface in default param	2012-12-06 17:34:48 +01:00
Sebastien Bourdeauducq	c3fdf42825	bus/csr: add SRAM	2012-12-06 17:16:17 +01:00
Sebastien Bourdeauducq	d4baac6c0f	bus/csr: allow specifying existing interface	2012-11-17 19:44:25 +01:00
Sebastien Bourdeauducq	4164fb4ac9	bus/csr: configurable data width	2012-08-26 21:19:34 +02:00
Sebastien Bourdeauducq	c82a468506	bus: CSR initiator	2012-07-07 22:36:15 +02:00
Sebastien Bourdeauducq	11674242c4	Use super() instead of calling parent constructors directly	2012-06-08 18:06:12 +02:00
Sebastien Bourdeauducq	0493212124	bus: simplify and cleanup ... Unify slave and master interfaces Remove signal direction suffixes Generic simple interconnect Wishbone point-to-point interconnect Description filter (get_name) Misc cleanups	2012-02-15 16:30:16 +01:00
Sebastien Bourdeauducq	8a61d9d121	bus/csr: Rename a->adr d->dat to be consistent with the other buses	2012-02-13 21:46:39 +01:00
Sebastien Bourdeauducq	a99c2acfa8	Remove explicit bus names and rely on the new automatic namer	2012-01-27 22:20:57 +01:00
Sebastien Bourdeauducq	566295dea3	csr: use optree	2011-12-22 19:36:56 +01:00
Sebastien Bourdeauducq	1a845d4553	32-device, 8-bit CSR bus	2011-12-17 15:54:49 +01:00
Sebastien Bourdeauducq	c7b9dfc203	fhdl: simpler syntax	2011-12-16 21:30:14 +01:00
Sebastien Bourdeauducq	39b7190334	Pay a bit more attention to PEP8	2011-12-16 16:02:55 +01:00
Sebastien Bourdeauducq	16a6029a1b	bus: fix CSR interconnect data readback	2011-12-11 20:17:12 +01:00
Sebastien Bourdeauducq	dad9120653	bus: 14-bit CSR addresses	2011-12-11 20:16:50 +01:00
Sebastien Bourdeauducq	7c99e51b90	Named buses	2011-12-08 19:16:08 +01:00
Sebastien Bourdeauducq	a6b86168ce	Simple bus base class	2011-12-08 18:47:32 +01:00
Sebastien Bourdeauducq	458cfc8623	CSR bus definitions	2011-12-05 00:16:44 +01:00