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8753 Commits

Author SHA1 Message Date
Florent Kermarrec ab8d906827 CHANGES.md: Update. 2023-03-30 10:13:56 +02:00
Florent Kermarrec 181d414911 integration/soc/add_pcie: Expose more DMA parameters. 2023-03-27 17:43:03 +02:00
enjoy-digital 4b72dd047e
Merge pull request #1662 from enjoy-digital/multi-channel-pwm 
soc/cores/pwm: Add MultiChannelPWM core reusing PWM module.
 2023-03-24 18:11:55 +01:00
enjoy-digital ffded272d4
Merge pull request #1655 from timkpaine/tkp/distfix 
Small packaging and CI changes
 2023-03-24 18:08:55 +01:00
Florent Kermarrec 4dabf0a330 cpu/vexriscv/naxriscv: Use reserved_interrupts to reserved interrupt 0. 2023-03-24 09:02:49 +01:00
Florent Kermarrec 2d24f50844 soc/add_cpu: Make sure to reserve CPU's reserved interrupt when adding CPU. 2023-03-24 09:02:22 +01:00
Florent Kermarrec e55f0da7c7 software/liblitesdcard: Only use sdcard_stop_transmission when nblocks > 1 (thanks @bayi). 
Similar to what is already done for reads.
 2023-03-24 08:39:50 +01:00
Gabriel Somlo c3e93620ec cpu/rocket: rework variant naming convention 
The naming convention for LiteX Rocket variants has become overly
complex. Simplify it while at the same time adding more flexibility.

There is a new set of instances of varying main RAM memory bus port
width (1x (64bit), 2x (128bit), 4x (256bit), and 8x (512bit)), of
each of the following principal LiteX specific Rocket models:

- small:  (rv64imac, no MMU, no S, no FPU)
- medium: (rv64imac, adds MMU and S-mode)
- linux:  (rv64imafdc, adds FPU, supports linux distros)
- full:   (rv64imafdcbkph[+], adds hypervisor support)

NOTE: before adding H support, the feature set of the old `full`
model is now represented by the `linux` model. The old `linux`
did not use to have an FPU, and is now available as `medium`.

In addition to the range of memory port widths, each model
will be instantiated in 1, 2, 4, and 8 core variants. The
naming convention is `LitexConfig_<model>_<num_cores>_<mem_width>`.

E.g. `LitexConfig_full_8_2` for an 8-core full model with
a 128bit main RAM AXI port. On the build command line, this
example would look like:

	...
	--cpu-type rocket --cpu-variant full \
	--cpu-num-cores 8 --cpu-mem-width 2 \
	...

There are a total of 4 * 4 * 4 = 64 (sub-)variants: each of the four
principal models can be fitted with one of four core counts, and one
of four memory bus widths.

Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
 2023-03-22 12:26:03 -04:00
Florent Kermarrec 5e5b929ee6 soc/cores/pwm: Add MultiChannelPWM core reusing PWM module. 
Also do minor changes to PWM module to allow reuse.
 2023-03-22 14:52:38 +01:00
enjoy-digital 1c43a71970
Merge pull request #1636 from gatecat/cva6_rv32 
CVA6: Adding RV32 support
 2023-03-22 12:06:52 +01:00
enjoy-digital 6274b0e9bf
Merge branch 'master' into cva6_rv32 2023-03-22 09:30:03 +01:00
enjoy-digital 6b362969e8
Merge pull request #1654 from shenki/rocket-cva6-csr 
cpu: rocket, cva6: Fix compilation with newer binutils
 2023-03-22 09:27:49 +01:00
Joel Stanley 71b522e5db cpu: rocket, cva6: Fix compilation with newer binutils 
Resolves the error:

 cpu/rocket/irq.h:23: Error: unrecognized opcode `csrr a4,mstatus',
 extension `zicsr' required

Rocket and cva6 missed this in commit 0e2a1b54a4 as they are 64bit
CPUs, and that change only updated the 32bit CPUs.

Tested with litex_sim and riscv64-unknown-elf-ld 2.40-2+4+b1 (Debian
Bookworm).

Signed-off-by: Joel Stanley <joel@jms.id.au>
 2023-03-22 17:41:46 +10:30
Tim Paine edbe8294b8 Simplify MANIFEST.in, include files relevant for distribution, add long 
description to setup.py, fix classifier tag, tweak CI to start
standardizing workflow
 2023-03-21 13:28:32 -04:00
enjoy-digital cd933da3ac
Merge pull request #1651 from trabucayre/gowinpll_complete_support 
soc/cores/clock/gowin_gw1n: add support for CLKOUTP, CLKOUTD, CLKOUTD3, phase and divisor
 2023-03-20 19:41:12 +01:00
Gwenhael Goavec-Merou 5f1a6026c8 soc/cores/clock/gowin_gw1n: add support for CLKOUTP, CLKOUTD, CLKOUTD3, phase and divisor 2023-03-20 08:00:03 +01:00
Florent Kermarrec 6ee39b4712 cores/cpu/vexriscv_smp/naxrisv: Fix/Shift IRQ numbering since 0 is reserved. 2023-03-17 21:33:37 +01:00
enjoy-digital 5f58753afe
Merge pull request #1650 from trabucayre/update_gowin_pll 
soc/cores/clock/gowin_gw1n: improve VCO configuration
 2023-03-17 18:25:49 +01:00
Gwenhael Goavec-Merou 94dfa81d65 soc/cores/clock/gowin_gw1n: improve VCO configuration 2023-03-17 11:12:35 +01:00
gatecat e50b5d0d45 cva6: Fix reset integration 
Signed-off-by: gatecat <gatecat@ds0.me>
 2023-03-15 16:14:19 +01:00
enjoy-digital cbf4db076e
Merge pull request #1648 from dalegaard/bugfix/litex_term_connect_timeout 
litex_term: improve connection setup
 2023-03-15 09:14:55 +01:00
gatecat 3ae3d66c80 cva6_wrapper: Fix reset logic 
Without this, reset was never being asserted which caused problems on
hardware (probably because the CPU started running while the rest of the
SoC had reset asserted...)

Signed-off-by: gatecat <gatecat@ds0.me>
 2023-03-14 13:03:20 +01:00
Florent Kermarrec d6db2be6b6 software/liblitedram: Halve seed_array (Calibration was too long on US(+) devices) and fix write latency calibration presentation when SDRAM_DELAY_PER_DQ is not set. 2023-03-14 12:09:10 +01:00
Lasse Dalegaard fe714f8fe7 litex_term: improve connection setup 2023-03-14 10:48:19 +01:00
Florent Kermarrec 38282effd4 soc/cores/bitbang: Cosmetic cleanups. 2023-03-14 09:51:56 +01:00
Florent Kermarrec c2c8504bec soc/cores/bitbang: Revert 1256ca3767. 2023-03-14 09:42:51 +01:00
enjoy-digital 341850939e
Merge pull request #1643 from jeremyherbert/bitbang-docs 
add docstrings to bitbang
 2023-03-14 09:36:38 +01:00
Jeremy Herbert 1256ca3767 small doc fixes, add type hints and PEP8 whitespace 2023-03-14 12:04:06 +10:00
enjoy-digital 9e08d96cb2
Merge pull request #1647 from te-johan/efinix_spi_mode 
build/efinix: add option use active or passive spi mode.
 2023-03-13 21:17:02 +01:00
enjoy-digital c2ea83db38
Merge pull request #1646 from Icenowy/gw2ar 
soc/cores/clock/gowin_gw2a: enable GW2AR support
 2023-03-13 21:12:00 +01:00
Johan Carlsson 60557b9e27 build/efinix: add option use active or passive spi mode. 2023-03-13 15:53:57 +01:00
Icenowy Zheng b05c306908 soc/cores/clock/gowin_gw2a: enable GW2AR support 
Gowin GW2AR is just GW2A with co-packaged external RAM.

Enable using GW2APLL for GW2AR.

Signed-off-by: Icenowy Zheng <uwu@icenowy.me>
 2023-03-13 16:46:31 +08:00
Jeremy Herbert c64c89c652 add docstrings to bitbang 2023-03-11 13:41:10 +10:00
Florent Kermarrec 67e8d77421 tools/litex_sim: Update Video Framebuffer. 2023-03-10 13:33:55 +01:00
Florent Kermarrec 7bd98cf5d9 tools/litex_json2dts_linux: Fix intc0 regression. 
Introduced when disabling lintc0 generation on Rocket.
 2023-03-10 09:34:00 +01:00
gatecat a31df7616f cva6: Fix SRAM compile on FPGA 
Signed-off-by: gatecat <gatecat@ds0.me>
 2023-03-09 12:20:37 +01:00
gatecat d137416739 cva6: Adding missing common_cells sources 
Signed-off-by: gatecat <gatecat@ds0.me>
 2023-03-09 11:49:07 +01:00
gatecat d90f8809b4 cva6: Improving JTAG debug support 
Signed-off-by: gatecat <gatecat@ds0.me>
 2023-03-09 11:49:07 +01:00
gatecat 6a73e4c5fb CVA6: Adding RV32 support 
Signed-off-by: gatecat <gatecat@ds0.me>
 2023-03-09 11:49:07 +01:00
enjoy-digital fb1cd22ac2
Merge pull request #1638 from gatecat/jtagremote_fix 
jtagremote: Add to Makefile and fix build
 2023-03-08 18:47:52 +01:00
Florent Kermarrec c2325983d5 litex_sim/video: Cleanup and directly reuse VideoGenericPHY. 2023-03-08 18:45:52 +01:00
gatecat a5d85518c9 jtagremote: Add to Makefile and fix build 
Signed-off-by: gatecat <gatecat@ds0.me>
 2023-03-08 13:06:16 +01:00
enjoy-digital c8dcc39957
Merge pull request #1632 from jorislee/master 
soc/cores/cpu/vexriscv_smp/core.py: fix variants for external incoming values and remove default timer0 and uart in standard mode.
 2023-03-06 09:03:55 +01:00
enjoy-digital 847fac0a81
Merge pull request #1631 from trabucayre/fix_get_extension 
add a proxy method to access bitstream extension
 2023-03-06 09:03:25 +01:00
Joris Lee 5c644aeabc
fix/VexRiscvSMP_Standard_mode_update 
Fix: VexRiscvSMP core variant defaults to incoming values and removes default timer0 and uart in standard mode.
 2023-03-06 14:17:12 +08:00
Gwenhael Goavec-Merou c40963531c build/generic_platform build/xxx/platform soc/integration/builder: 
generic_platform add a method to return extension for sram/flash
vendor platform: bitstream_ext -> _bitstream_ext and replace by a dict
when extension depends on mode
builder: use `get_bitstream_extension` instead of directly using
bitstream_ext
 2023-03-04 11:36:29 +01:00
Gwenhael Goavec-Merou 1ea94ca264 build/anlogic/platform: fix extension format fs -> bit 2023-03-04 11:25:46 +01:00
enjoy-digital 2d9c880cf2
Merge pull request #1629 from trabucayre/fix_efinix_ifacewriter 
build/efinix/efinity: delays iface.py execution after project xml was written
 2023-03-02 09:14:08 +01:00
Gwenhael Goavec-Merou b28598289e build/efinix/efinity: delays iface.py execution after project xml was written 2023-03-02 08:42:59 +01:00
Florent Kermarrec ea2171d32b tools/litex_sim: Fix --with-etherbone --with-ethernet case (thanks @g2gps). 2023-03-01 14:49:08 +01:00