b6fe3ace05
fhdl/structure: style fix
2013-03-17 15:33:38 +01:00
2a4cc3875c
Merge pull request #6 from larsclausen/master
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Minor improvements
2013-03-17 07:33:14 -07:00
7b49fd9386
fhdl/specials: fix rename_clock_domain declarations
2013-03-15 19:47:01 +01:00
dd0f3311cd
structure: remove Fragment.call_sim
2013-03-15 19:15:48 +01:00
bd8bbd9305
Make ClockDomains part of fragments
2013-03-15 18:17:33 +01:00
72579a6129
Add support for negative slice indices
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In python a negative indices usually mean start counting from the right side.
I.e. if the index is negative is acutal index used is len(l) + i. E.g. l[-2]
equals l[len(l)-2].
Being able to specify an index this way also comes in handy for migen slices in
some cases. E.g. the following snippet can be implement to shift an abitrary
length register n bits to the right:
reg.eq(Cat(Replicate(0, n), reg[-n:])
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2013-03-12 21:56:01 +01:00
ecfe1646ec
fhdl/verilog: implicit get_fragment
2013-03-12 16:16:06 +01:00
4ada2ead05
fhdl/specials/Memory: automatic name#
2013-03-12 15:58:39 +01:00
04df076fba
bank: automatic register naming
2013-03-12 15:45:24 +01:00
7e2581bf17
fhdl/tracer: recognize CALL_FUNCTION_VAR opcode
2013-03-12 13:48:09 +01:00
12158ceadf
fhdl/tracer: recognize LOAD_DEREF opcode
2013-03-12 10:31:56 +01:00
3c75121783
fhdl/tracer: remove leading underscores from names
2013-03-11 22:21:58 +01:00
17e0dfe120
fhdl/module: replace autofragment
2013-03-10 19:27:55 +01:00
d0676e2dd1
migen/fhdl/autofragment: factorize
2013-03-09 23:23:24 +01:00
d0d2df3c4b
fhdl/autofragment: remove legacy functions
2013-03-09 23:05:45 +01:00
72fb6fd6bd
fhdl/tools/flat_iteration: generalize
2013-03-09 23:03:15 +01:00
f53acb92e7
fhdl/autofragment: fix submodules
2013-03-09 21:15:38 +01:00
6da8eb906f
fhdl/autofragment: empty build_fragment by default
2013-03-09 19:10:47 +01:00
2b8dc52c13
Use common definition for FinalizeError
2013-03-09 19:03:13 +01:00
6fa30053bf
fhdl/verilog: tristate outputs are always wire
2013-03-06 11:30:52 +01:00
bb5ee8d3bd
fhdl/autofragment: bugfixes + add auto_attr
2013-03-03 17:53:06 +01:00
cc8118d35c
fhdl/autofragment: FModule
2013-03-02 23:30:54 +01:00
c10622f5e2
fhdl/verilog: insert reset before listing signals
2013-02-27 18:10:04 +01:00
a81781f589
fhdl/specials: allow setting memory name
2013-02-25 23:14:03 +01:00
55ab01f928
fhdl/specials/Instance: _printintbool -> verilog_printexpr
2013-02-24 13:08:01 +01:00
7c4e6c35e5
fhdl/verilog: support special lowering and overrides
2013-02-23 19:03:16 +01:00
38664d6e16
fhdl: inline synthesis directive support
2013-02-22 19:10:02 +01:00
49cfba50fa
New 'specials' API
2013-02-22 17:56:35 +01:00
1b18194b1d
fhdl: TSTriple
2013-02-19 17:26:02 +01:00
dc93a231c6
fhdl: tristate support
2013-02-15 00:17:24 +01:00
63d399b6ad
fhdl/autofragment: from_attributes
2013-02-11 18:34:01 +01:00
473fd20f8c
fhdl/structure: store clock domain name
2013-01-24 13:49:49 +01:00
3201554f76
fhdl/verilog: fix spurious clock/reset signals on multiple calls to convert()
2013-01-23 15:13:06 +01:00
badba89686
fhdl: support nested statement lists
2013-01-05 14:18:15 +01:00
3fae6c8f03
Do not use super()
2012-12-18 14:54:33 +01:00
b06fbdedd6
fhdl/tools: bitreverse
2012-12-14 23:56:16 +01:00
483b821342
fhdl/structure: do not create Signal in Instance when parameter is int
2012-12-06 20:56:46 +01:00
70e97e0456
Fix various errors from new bitwidth/signedness system conversion
2012-11-29 23:36:55 +01:00
261166d92b
fhdl/verilog: make signal behave as integers in arithmetic (MyHDL style)
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See http://jandecaluwe.com/hdldesign/counting.html
2012-11-29 22:59:54 +01:00
55d143a454
fhdl/structure: add unary minus
2012-11-29 22:52:57 +01:00
50ed73c937
New specification for width and signedness
2012-11-29 21:22:38 +01:00
6eebfce44a
Refactor Case
2012-11-29 01:11:15 +01:00
fee22a4631
Remove Constant
2012-11-28 23:18:43 +01:00
59831e0485
fhdl/structure: improved bits_for function
2012-11-28 18:39:44 +01:00
11b1e53224
visit/NodeTransformer: copy most nodes
2012-11-28 17:50:55 +01:00
a2bcbfdf8f
fhdl/tools: use NodeTransformer to lower arrays
2012-11-28 17:46:15 +01:00
3bc15024ac
fhdl/tools: use NodeVisitor
2012-11-26 21:40:23 +01:00
1460f069f6
fhdl/structure: remove deprecated MemoryPort
2012-11-26 19:36:43 +01:00
27d87c9412
fhdl/structure: disable we_granularity when larger than width
2012-11-23 23:08:12 +01:00
f42683b71e
fhdl/structure/Memory: fix we width
2012-11-23 19:21:52 +01:00
0f6215a13a
fhdl/structure: add Memory.get_port API
2012-11-23 19:17:49 +01:00
9d3e218863
fhdl: use object creation counter (HUID) as hash. This finally makes the generated code textually the same across runs.
2012-11-23 18:38:03 +01:00
3971600917
fhdl/structure: use sets for memories and instance collections
2012-11-23 17:20:08 +01:00
51e2e6ecd0
fhdl/verilog: remove empty cases
2012-11-18 16:32:51 +01:00
26cf1b8840
fhdl: make constants hashable
2012-11-09 20:17:43 +01:00
7744655ef2
fhdl/visit: add missing self
2012-11-09 17:37:24 +01:00
13af0ce556
fhdl: visit module (untested)
2012-11-09 16:00:11 +01:00
56d4cdeb48
fhdl/structure: make all values hashable
2012-11-06 13:51:51 +01:00
8101b68965
fhdl: fix instance get_io
2012-09-28 18:02:03 +02:00
c273866b08
fhdl: support expressions in instance ports
2012-09-22 20:51:10 +02:00
2fc9cae88a
fhdl: support inverted clock ports in instances
2012-09-22 20:50:49 +02:00
2e14569b5c
fhdl/verilog: sort clock domains by name
2012-09-11 10:00:03 +02:00
9a18a9df3f
fhdl: list signals in execution order
2012-09-11 09:59:37 +02:00
e16353a281
Multi-clock design support + new instance API
2012-09-10 23:45:02 +02:00
b45c9546eb
fhdl/namer: better handling of indices
2012-09-09 19:33:55 +02:00
589251fffd
fhdl/tracer: support BUILD_LIST opcode
2012-09-09 18:53:24 +02:00
910c350021
fhdl/namer: use execution order indices for variable names as well
2012-09-09 17:31:35 +02:00
f3e3a3eec7
fhdl/namer: number objects according to execution order
2012-09-09 12:27:32 +02:00
51f9a2a963
fhdl/namer: simplify + more relevant names
2012-09-09 01:26:33 +02:00
8de192dfbd
x.bv.width -> len(x)
2012-07-13 18:32:54 +02:00
9cdc88eadf
fhdl: len() for Constant
2012-07-13 18:16:50 +02:00
599ed8d470
fhdl: fix value_bv for operators
2012-07-13 17:40:49 +02:00
7f47a2568a
fhdl: remove _StatementList
2012-07-13 17:07:56 +02:00
eed8fa374d
fhdl/arrays: use correct BV for intermediate signals
2012-07-11 12:06:32 +02:00
ed27783a53
fhdl: arrays (TODO: use correct BV for intermediate signals)
2012-07-09 15:16:38 +02:00
398ece8fe2
fhdl/verilog: add option to display which comb blocks are run
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This is a debug hack to help find combinatorial loops in designs.
2012-04-30 16:38:40 -05:00
6a52e44d09
fhdl: support len() on signals
2012-04-08 18:06:22 +02:00
2a4e49e381
fhdl: phase out pads
2012-04-02 19:21:43 +02:00
623e8e436a
fhdl/verilog: do not attempt to initialize instance and mem output signals
2012-04-02 12:59:42 +02:00
f3ae22f488
fhdl/verilog: initialize internal read-only signals with their reset values
2012-04-01 16:39:11 +02:00
5c0cc6292c
fhdl: export log2_int
2012-03-14 12:19:42 +01:00
bfcd4e636b
fhdl: handle negative constants correctly
2012-03-08 20:49:24 +01:00
98e96b3952
sim: make initialization cycle optional (selectable by function attribute)
2012-03-06 19:43:59 +01:00
8160ced2e9
sim: memory access
2012-03-06 19:29:39 +01:00
db8f8bf2e3
fhdl: register memory objects with namespace
2012-03-06 18:33:44 +01:00
90184b22d2
fhdl/verilog: fix signed constant conversion
2012-03-06 16:45:44 +01:00
7230508e7c
fhdl/namer: do not reference objects with __del__ methods to avoid uncollectable cycles
2012-03-06 14:18:22 +01:00
8d16fde48c
fhdl: add simulation functions in fragment
2012-03-06 13:58:22 +01:00
f995e8b92e
fhdl: check we pass BV to signals
2012-02-17 23:50:54 +01:00
a1ad30faab
fhdl/verilog: properly connect instance inouts
2012-02-17 11:08:41 +01:00
ca7056b07f
fhdl: support forwarding of bidirectional signals from instance ports
2012-02-16 18:34:32 +01:00
1eb348c573
fhdl: do not attempt slicing non-array signals to keep Verilog happy
2012-02-06 18:07:02 +01:00
629e771fc0
fhdl/structure: binary constant builder
2012-02-05 19:32:11 +01:00
2b3f00cbc1
fhdl/namer: Add support for STORE_DEREF opcode
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Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2012-02-02 21:15:10 +01:00
6a9b59786b
fhdl/namer: extract variable names with bytecode inspection
2012-01-28 23:17:44 +01:00
5c2df45577
fhdl: do not prefix instance signal names
2012-01-28 11:39:28 +01:00
685b5eb08f
fhdl: support memory read enable
2012-01-27 21:39:23 +01:00
0cc7e2ac1e
fhdl: make WRITE_FIRST default
2012-01-27 21:35:58 +01:00
5405a83ff9
fhdl: memories working
2012-01-27 20:22:17 +01:00
a5bd111370
fhdl/verilog: clean up signal classification and support memory descriptions
2012-01-27 16:54:48 +01:00
Sebastien Bourdeauducq
Lars-Peter Clausen