b32a0e6f9e
liteeth: create example design derived from SoC that can be used on all targets with Ethernet pins
2015-02-28 23:33:00 +01:00
6107b7844a
test implementation on all targets and fix issues
2015-02-28 12:04:51 +01:00
1366ff5e26
move mxcrg to others (we should integrate it in mlabs_video.py and remove the verilog file in the future)
2015-02-28 11:51:51 +01:00
69e869893d
remane GenSoC to SoC (more coherent and we will add support for multiple SoCs with their own Wisbbone/CSR buses in the future)
2015-02-28 11:36:15 +01:00
2c51adcd68
misoclib: better organization (create cores categories: cpu, mem, com, ...)
2015-02-28 09:40:44 +01:00
074f576340
targets: add de0nano (100MHz, integrated bios and SDRAM)
2015-02-27 19:47:32 +01:00
5e2e9338d2
bios: we can now use -Ot with_rom True on targets to force bios implementation in integrated rom (can speed up debug we don't want to reflash SPI or NOR flash)
2015-02-27 17:22:44 +01:00
b031c5edae
targets: fix MiniSoC
2015-02-27 17:12:37 +01:00
07b9cabd0d
gensoc: make it more generic (a SoC does not necessarily have a CPU)
2015-02-27 16:39:00 +01:00
367db268ad
reserve csr_map 0-->16 for gensoc internal csrs
2015-02-27 14:18:13 +01:00
77a6f580e2
gensoc: add check_cpu_memory_region and check_csr_region to detect csr and mem regions conflicts
2015-02-27 10:23:02 +01:00
2b12679ef6
add pipistrello target
2015-02-26 21:35:42 -07:00
a3909bb5e2
Merge branch 'master' of https://github.com/m-labs/misoc
2015-02-26 21:28:12 -07:00
8364fe6674
target/kc705: allow access to pll_sys signal before BUFG
2015-02-26 15:56:10 -07:00
5e8a0c496d
gensoc: add mem_map and mem_decoder to avoid duplications
2015-02-26 20:12:27 +01:00
554731ae44
targets/simple: make it generic (no default_platform, use platform's default_clk_name/default_clk_period)
2015-02-26 13:08:15 +01:00
00862a383c
liteeth: fix import (from liteeth --> from misoclib.liteeth)
2015-02-26 09:48:37 +01:00
73ab271f9a
targets/kc705: fix csr address conflict on eth
2015-02-18 10:45:18 -07:00
0a38b8c74a
add LiteX external core and remove ethmac
2015-02-18 10:43:44 -07:00
9ebb8f8022
remove verilog and move mxcrg.v to misoclib/mxcrg
2015-02-18 10:40:30 -07:00
ceb675c3f1
fix cf92821 merge issue
2014-12-19 21:49:49 +08:00
edb1622668
spiflash: BB write support
2014-11-27 23:10:39 +08:00
cf92821fcf
Refactor directory hierarchy of sdram phys and controllers
2014-11-27 22:09:10 +08:00
33530e0921
ethmac: style/renaming
2014-11-20 18:01:48 -08:00
7eaa5f7372
targets/kc705: avoid ddrphy/ethphy address conflict
2014-11-20 17:11:57 -08:00
603c2641bb
new Ethernet MAC
2014-11-20 16:47:22 -08:00
13fb9282db
targets: add simple design (vendor agnostic and usable on all platforms with UART pins).
...
Designing a SoC with Migen is easy, but we have to provide a very simple design that can
be used on all boards with only 1 clock and 2 UARTs pins defined. This will encourage the
newcomer to invest time in Migen/MiSoC and see its real potential.
2014-09-26 10:35:15 +08:00
c0c17030fd
spi_flash: simplify usage by removing cmd, cmd_width, addr_width parameters
2014-09-04 15:23:39 +08:00
0eeb0ad9eb
targets/kc705: add ddrphy to CSR map
2014-09-01 16:40:10 +08:00
35327a427f
targets/kc705: BIOS XIP
2014-08-22 17:13:10 +08:00
6b35c7b8ea
targets/ppro: reduce SPI flash clock frequency
2014-08-22 15:24:14 +08:00
7b10f1821f
targets/ppro: fix BIOS address
2014-08-22 15:24:00 +08:00
2f2a57dd34
targets/ppro: clean up indentation
2014-08-22 14:41:28 +08:00
41c8c172b5
targets/kc705: integrate DDR3
2014-08-08 21:58:41 +08:00
fb48b89bac
platforms/kc705: generate clocks for SDRAM
2014-08-06 23:53:26 +08:00
ca6d6954c1
targets/ppro: use migen reset synchronizer
2014-08-06 19:38:11 +08:00
37968e649b
targets/kc705: use PLL for clocking
2014-08-03 21:42:39 +08:00
f7a7137127
targets: add basic KC705
2014-08-03 15:48:30 +08:00
213cb43ae5
Keep only basic SoC designs in MiSoC
2014-08-03 12:30:15 +08:00
ac97815619
targets/simple: pass kwargs
2014-05-24 11:29:03 +02:00
e9b49ebb44
Use SDRAM on the Papilio Pro
...
Based on code by Robert Jordens
2014-05-23 21:26:09 +02:00
6298624f98
sdramphy: remove fixed parameters
2014-05-14 16:08:40 +02:00
94b2295a96
targets/mlabs_video: pass with_memtest as kwargs
2014-05-14 15:02:07 +02:00
1c08aeb21c
Initial mor1kx (OpenRISC) support
...
Based on milkymist-ng-mor1kx by Stefan Kristiansson
2014-05-14 10:24:56 +02:00
41c35e7e0c
simple: create PowerOnRst and use it (remove vendor-dependent code)
2014-04-17 19:39:05 +02:00
1adceb8276
sdramphy: move and clean up s6ddrphy, add generic SDRAM PHY
2014-04-17 19:38:25 +02:00
362f938736
simplesoc: free LED
2014-04-14 00:23:41 +02:00
0c3f8f703d
targets/simple: add dummy SDRAM + flash boot address
2014-04-08 15:25:49 +02:00
9e784fc82c
Generate mem.h from SoC description
2014-02-21 17:55:05 +01:00
fce46ac0ca
Simplify use of external targets/platforms/cores + add default platform in targets
2014-02-16 14:51:52 +01:00
Florent Kermarrec
Robert Jordens
Sebastien Bourdeauducq
Yann Sionneau
Sebastien Bourdeauducq