Florent Kermarrec
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b32a0e6f9e
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liteeth: create example design derived from SoC that can be used on all targets with Ethernet pins
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2015-02-28 23:33:00 +01:00 |
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Florent Kermarrec
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b34be816ec
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liteXXX cores: remove setup.py and relative paths (we will install misolib of use PYTHON_PATH)
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2015-02-28 22:23:48 +01:00 |
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Florent Kermarrec
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5c43d4d091
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litescope: create example design derived from SoC that can be used on all targets
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2015-02-28 22:19:24 +01:00 |
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Florent Kermarrec
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0fd1b9df8d
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liteXXX cores: remove redefinition of get_csr_csv
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2015-02-28 21:45:05 +01:00 |
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Florent Kermarrec
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5bd1ab7fa1
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liteXXX cores: update README and doc
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2015-02-28 21:40:59 +01:00 |
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Florent Kermarrec
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165a5b6760
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soc: use self.cpu_reset_address as rom mem_map address and increase default bios size to 0xa000
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2015-02-28 20:04:51 +01:00 |
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Florent Kermarrec
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6107b7844a
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test implementation on all targets and fix issues
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2015-02-28 12:04:51 +01:00 |
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Florent Kermarrec
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1366ff5e26
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move mxcrg to others (we should integrate it in mlabs_video.py and remove the verilog file in the future)
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2015-02-28 11:51:51 +01:00 |
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Florent Kermarrec
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8564b7eb6a
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soc: move SDRAMSoC to a separate sdram.py file (ideally part of SDRAMSoC should move mem/sdram)
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2015-02-28 11:44:14 +01:00 |
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Florent Kermarrec
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69e869893d
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remane GenSoC to SoC (more coherent and we will add support for multiple SoCs with their own Wisbbone/CSR buses in the future)
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2015-02-28 11:36:15 +01:00 |
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Florent Kermarrec
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912573f5c9
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liteusb: move files and modify import to misoclib.com.liteusb
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2015-02-28 11:18:00 +01:00 |
|
Florent Kermarrec
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b647fe5823
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merge liteusb
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2015-02-28 11:16:16 +01:00 |
|
Florent Kermarrec
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8e67d6e69f
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liteeth: fix example design generation and remove VivadoProgrammer from platfom. (TODO: remove others duplicates)
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2015-02-28 11:08:17 +01:00 |
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Florent Kermarrec
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2c3e8a2804
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liteeth: fix example design generation and remove VivadoProgrammer from platfom. (TODO: remove others duplicates)
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2015-02-28 11:04:48 +01:00 |
|
Florent Kermarrec
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0dfca49e68
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litesata: move file and modify import to misoclib.mem.litesata
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2015-02-28 11:03:24 +01:00 |
|
Florent Kermarrec
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b6358be0a1
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merge litesata
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2015-02-28 10:48:08 +01:00 |
|
Florent Kermarrec
|
df0ba1b03c
|
litescope: create example_designs directory
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2015-02-28 10:42:12 +01:00 |
|
Florent Kermarrec
|
c4ebf244a1
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litescope: move files and modify import to misoclib.tools.litescope
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2015-02-28 10:33:46 +01:00 |
|
Florent Kermarrec
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b274e948dc
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merge litescope
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2015-02-28 10:24:49 +01:00 |
|
Florent Kermarrec
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a43c555ee3
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misoclib/com: add spi (only SPIMaster for now)
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2015-02-28 09:43:03 +01:00 |
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Florent Kermarrec
|
2c51adcd68
|
misoclib: better organization (create cores categories: cpu, mem, com, ...)
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2015-02-28 09:40:44 +01:00 |
|
Florent Kermarrec
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6b93849a08
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gensoc: parameter check is now more restrictive, add additional info to help user
|
2015-02-28 03:12:00 +01:00 |
|
Florent Kermarrec
|
8e04ef7b95
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test minicon with de0nano (OK) and fix missing self in gensoc
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2015-02-27 20:00:16 +01:00 |
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Florent Kermarrec
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f1200d6388
|
gensoc: move I/O for rom initialization to make.py
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2015-02-27 19:48:07 +01:00 |
|
Florent Kermarrec
|
074f576340
|
targets: add de0nano (100MHz, integrated bios and SDRAM)
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2015-02-27 19:47:32 +01:00 |
|
Florent Kermarrec
|
cb38580400
|
make.py fix indent
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2015-02-27 18:58:36 +01:00 |
|
Florent Kermarrec
|
5e2e9338d2
|
bios: we can now use -Ot with_rom True on targets to force bios implementation in integrated rom (can speed up debug we don't want to reflash SPI or NOR flash)
|
2015-02-27 17:22:44 +01:00 |
|
Florent Kermarrec
|
b031c5edae
|
targets: fix MiniSoC
|
2015-02-27 17:12:37 +01:00 |
|
Florent Kermarrec
|
e07e124118
|
sdram: import dfi, lasmibus, wishbone2lasmi from Migen in sdram/bus dir
We will maybe move things, but at least it's in MiSoC now
|
2015-02-27 17:07:44 +01:00 |
|
Florent Kermarrec
|
07b9cabd0d
|
gensoc: make it more generic (a SoC does not necessarily have a CPU)
|
2015-02-27 16:39:00 +01:00 |
|
Florent Kermarrec
|
367db268ad
|
reserve csr_map 0-->16 for gensoc internal csrs
|
2015-02-27 14:18:13 +01:00 |
|
Florent Kermarrec
|
be0eb8d265
|
use cachesize reported in wishbone2lasmi
|
2015-02-27 14:13:38 +01:00 |
|
Florent Kermarrec
|
9814001c79
|
create cpu dir and move lm32/mor1kx in it
|
2015-02-27 10:51:03 +01:00 |
|
Florent Kermarrec
|
9f636f7985
|
move memtest to sdram
|
2015-02-27 10:47:54 +01:00 |
|
Florent Kermarrec
|
b817cf49b3
|
replace self._r_register by self._register in all CSR declaration
|
2015-02-27 10:36:09 +01:00 |
|
Florent Kermarrec
|
e4de5a0c9d
|
make.py: avoid some actions in make all (do not flash if load-bitstream is specified or if bios is in blockram)
|
2015-02-27 10:23:17 +01:00 |
|
Florent Kermarrec
|
77a6f580e2
|
gensoc: add check_cpu_memory_region and check_csr_region to detect csr and mem regions conflicts
|
2015-02-27 10:23:02 +01:00 |
|
Florent Kermarrec
|
617bc70d7f
|
liteeth: move doc
|
2015-02-27 09:15:54 +01:00 |
Robert Jordens
|
2b12679ef6
|
add pipistrello target
|
2015-02-26 21:35:42 -07:00 |
|
Robert Jordens
|
c9ed38dec8
|
gensoc: missing self.
|
2015-02-26 21:32:11 -07:00 |
Sebastien Bourdeauducq
|
a3909bb5e2
|
Merge branch 'master' of https://github.com/m-labs/misoc
|
2015-02-26 21:28:12 -07:00 |
Yann Sionneau
|
8364fe6674
|
target/kc705: allow access to pll_sys signal before BUFG
|
2015-02-26 15:56:10 -07:00 |
|
Florent Kermarrec
|
09fbbca53e
|
gensoc: cpus now directly add their verilog sources
|
2015-02-26 20:49:21 +01:00 |
|
Florent Kermarrec
|
5e8a0c496d
|
gensoc: add mem_map and mem_decoder to avoid duplications
|
2015-02-26 20:12:27 +01:00 |
|
Florent Kermarrec
|
5ac5ffe359
|
gensoc: get platform_id from platform
|
2015-02-26 19:07:19 +01:00 |
|
Florent Kermarrec
|
554731ae44
|
targets/simple: make it generic (no default_platform, use platform's default_clk_name/default_clk_period)
|
2015-02-26 13:08:15 +01:00 |
|
Florent Kermarrec
|
02b3f51382
|
liteeth: fix example_designs generation
|
2015-02-26 10:23:38 +01:00 |
|
Florent Kermarrec
|
00862a383c
|
liteeth: fix import (from liteeth --> from misoclib.liteeth)
|
2015-02-26 09:48:37 +01:00 |
|
Florent Kermarrec
|
60effe1d95
|
move files to liteeeth and create example_designs directory
|
2015-02-26 09:35:14 +01:00 |
|
Sebastien Bourdeauducq
|
0267868cbe
|
remove litex submodule
|
2015-02-25 10:40:44 -07:00 |