Commit Graph

4924 Commits

Author SHA1 Message Date
bunnie b3f9aa11be add option for BUFGCE to the clock generator buffer types 2020-01-24 14:58:51 +08:00
bunnie eae0e00496 cores/clock/xadc: ease DRP timings
Hard IP blocks are fixed in location, so long/deep combinational paths routing to multiple hard IP blocks can lead to timing closure problems.

XADC and MMCM DRPs currently have their DEN pins triggered by the ".re" output of a CSR. This is asynchronously derived from a fairly complicated set of logic that involves a logic path that goes all the way back through the cache and arbitration mechanisms of the wishbone bus. On more complex designs, this is leading to a failure of timing closure for these paths, because the hard IP blocks can be located in disparate portions of the chip which "pulls" the logic cluster in opposite directions in an attempt to absorb the routing delays to these IP blocks, leading to non-optimal placement for everything else and thus timing closure problems.

This pull request proposes that we add a pipeline delay on these critical paths. This delays the commit of the data to the DRP by one cycle, but greatly relieves timing because the pipeline register can be placed close to the cluster of logic that computes addresses, caching, and arbitration, allowing for the routing slack to the hard IP blocks to be absorbed by the path between the pipe register and the hard IP block.

In general, this shouldn't be a problem because the algorithm to program the DRP is to hit the write or read CSR, and then poll the drdy bit until it is asserted (so the process is already pretty slow). The MMCM in particular should have almost no impact, because MMCM updates are infrequent and the subsequent lock time of the MMCM is pretty long. The XADC is potentially more problematic because it can produce data at up to 1MSPS; but if sysclk is around 100MHz, adding 10ns to the read latency is relatively small compared to the theoretical maximum data rate of one every 1,000ns.

Note that the xadc patch requires introducing a bit of logic into the non-DRP path. This is because without explicitly putting an "if" statement around the logic, you fall back to the non-blocking semantics of the verilog operator, which ultimately leads to a pretty hefty combinational path. By having a default "if" that should get optimized out when DRP is not enabled, when the DRP path /is/ enabled the synthesizer knows it can safely push the async signal into a simple mux as opposed to worrying about enforcing the non-blocking operator semantics to get the desired result.
2020-01-19 20:57:14 +01:00
Florent Kermarrec 7b92a17c6e test/test_targets: limit max_sdram_size to 1GB 2020-01-17 13:24:45 +01:00
Florent Kermarrec 008a089471 targets/nexys4ddr: fix typo 2020-01-17 13:17:08 +01:00
Florent Kermarrec 36e5274a2b SoCSDRAM: set default max_sdram_size to 1GB (maximum we can map with current mem_map) 2020-01-17 12:45:23 +01:00
Florent Kermarrec 46c1c5c16f targets/kcu105: remove main_ram_size_limit 2020-01-17 12:27:21 +01:00
Florent Kermarrec 5913c91caa SoCSDRAM: rename main_ram_size_limit to max_sdram_size and make it a parameter of SoCSDRAM, expose SoCSDRAM parameters to user 2020-01-17 12:16:08 +01:00
Florent Kermarrec 1c465f89b6 build/lattice: add add_false_path_constraint method for API compatibility but false paths are not yet used/translated to .lpf file 2020-01-17 10:17:19 +01:00
Florent Kermarrec b4ba2a47ef soc/cores/uart: set rx_fifo_rx_we to True on UARTCrossover 2020-01-17 06:32:00 +01:00
Florent Kermarrec 5aa516cb8d soc/cores/uart: add rx_fifo_rx_we parameter to pulse rx_fifo.source.ready on rxtx register read.
When UARTCrossover is used over Etherbone, acking data directly with the read avoid the write/read round-trip
and speed up communication a lot (>10x).
2020-01-16 19:45:41 +01:00
Florent Kermarrec 862e784eae cpu/vexriscv: use 32-bit signal for externalResetVector 2020-01-16 16:20:25 +01:00
Florent Kermarrec f2a1673f46 targets/arty/genesys2: fix EthernetSoC/EtherboneSoC selection 2020-01-16 13:17:33 +01:00
Florent Kermarrec 990870d061 targets/genesys2: add EtherboneSoC 2020-01-16 12:32:59 +01:00
Florent Kermarrec 820e79bf9c platforms/de0nano: specify gpio for serial 2020-01-16 12:32:25 +01:00
Florent Kermarrec ba366d42d0 targets: cleanup EthernetSoC 2020-01-16 10:14:42 +01:00
Florent Kermarrec a26853702c soc/interconnect/packet/Depacketizer: use both sink.valid and sink.ready to update sink_d, fix Etherbone regression on Arty. 2020-01-16 09:46:54 +01:00
Florent Kermarrec a168ecbabd targets/arty: add EtherboneSoC 2020-01-16 09:11:44 +01:00
Florent Kermarrec 7a4ecfa59d targets/kcu105: update 2020-01-15 13:17:59 +01:00
Florent Kermarrec 68e225fb45 test/test_targets: update 2020-01-15 13:09:03 +01:00
Florent Kermarrec 42efa99826 SoCCore: set default integrated_rom/ram_size to 0. For targets, defaults values are provided by soc_core_args. 2020-01-15 10:59:01 +01:00
Florent Kermarrec 4050e60834 SoCCore: use hex for integrated_rom/sram_size 2020-01-13 20:01:45 +01:00
enjoy-digital f818755c9c
Merge pull request #339 from gsomlo/gls-csr-cleanup
CSR Improvements and Cleanup
2020-01-13 19:57:59 +01:00
Florent Kermarrec f1606dbc72 tools/litex_sim: use default integrated_rom_size 2020-01-13 17:39:23 +01:00
Florent Kermarrec 4648db0c2a cores/uart/UARTInterface: remove connect method 2020-01-13 16:58:00 +01:00
Florent Kermarrec 6c9f418d26 soc_core: fix uart stub 2020-01-13 16:56:31 +01:00
Gabriel Somlo b073ebadf6 bios/sdram: switch to updated CSR accessors, and misc. cleanup
Revert to treating SDRAM_DFII_PIX_[RD|WR]DATA CSRs as arrays
of bytes, but use the new uintX_t array accessors for improved
legibility, and to avoid unnecessary byteswapping.

Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
2020-01-13 10:09:02 -05:00
Gabriel Somlo 2c39304110 software, integration/export: rename and reimplement CSR accessors
Implement CSR accessors for all standard integer types and
combinations of subregister alignments (32 or 64 bit) and
sizes (i.e., csr_data_width 8, 16, or 32).

Rename accessors to better reflect the size of the register
being accessed, and correspondingly update the generation
of "csr.h" in "export.py".

Additionally, provide read/write accessors that superimpose arrays
of standard unsigned C types over a CSR register (which may itself
be spread across multiple subregisters).

Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
2020-01-13 10:09:02 -05:00
Florent Kermarrec 63cd23c9c3 cpu/vexriscv: revert mem_map_linux/main_ram 2020-01-13 16:02:32 +01:00
Florent Kermarrec 83a7225ccc SoCCore: set integrated rom/sram size default values in soc_core_args and use it in targets 2020-01-13 15:03:36 +01:00
Florent Kermarrec 6e3f25a7e0 cpu/vexriscv/mem_map_linux: update main_ram to 0x40000000 2020-01-13 14:40:26 +01:00
Florent Kermarrec fe14b9cf86 targets/genesys2: update self.register_sdram 2020-01-13 14:39:45 +01:00
Florent Kermarrec 39ce39a298 soc_sdram: add l2_data_width parameter to set minimal l2_data_width to improve DRAM accesses efficiency. 2020-01-13 13:00:17 +01:00
Florent Kermarrec 23175190d8 cores/uart: add UARTCrossover 2020-01-13 10:14:38 +01:00
Florent Kermarrec 2f03d3234e cores/uart/UART: add stream interface (phy=None), add connect method and use this for UART Stub/Crossover.
A bridged/crossover UART can now just be created by:
- passing uart_name="stream" to SoCCore/SoCSDRAM.
- adding a crossover UART core to the design:

# UART Crossover (over Wishbone Bridge
from litex.soc.cores.uart import UART
self.submodules.uart_xover = UART(tx_fifo_depth=2, rx_fifo_depth=2)
self.add_csr("uart_xover")
self.comb += self.uart.connect(self.uart_xover)
2020-01-13 09:20:40 +01:00
Florent Kermarrec d92bd8ffaa gen/fhdl/verilog: fix signed init values 2020-01-12 22:06:35 +01:00
enjoy-digital ff066a5e09
Merge pull request #338 from DurandA/master
Add optional 'ignore-loops' flag to nextpnr
2020-01-12 21:18:23 +01:00
Florent Kermarrec 26fe45fce1 cores/uart: rename BridgedUART to UARTEmulator and rework/simplify it. Also integrated it in SoCCore with uart_name="emulator" 2020-01-12 21:13:02 +01:00
enjoy-digital d40bf9d8a7
Merge pull request #340 from xobs/bridged-uart
uart: add BridgedUart
2020-01-12 20:40:27 +01:00
Sean Cross 5079a3c32e uart: add BridgedUart
This version of the UART adds a second, compatible UART after
the first.  This maintians software compatibility, and allows a
program running on the other side of the litex bridge to act as
a terminal emulator by manually reading and writing the second
UART.

Signed-off-by: Sean Cross <sean@xobs.io>
2020-01-12 19:52:42 +10:00
Arnaud Durand d24a4b5428 Add optional 'ignore-loops' flag to nextpnr 2020-01-10 16:07:56 +01:00
Florent Kermarrec f70dd48279 bios/sdram: add memspeed 2020-01-10 14:25:46 +01:00
Florent Kermarrec fa22d6aa82 wishbone/Cache: avoid REFILL_WRTAG state to improve speed. 2020-01-10 14:25:07 +01:00
Florent Kermarrec f408527dd4 soc/cores/cpu: add riscv64-linux toolchain support for risc-v cpus.
Toolchain can be downloaded from https://toolchains.bootlin.com/
2020-01-10 08:49:34 +01:00
Florent Kermarrec 8889821c54 targets: sync with litex-boards 2020-01-09 21:12:00 +01:00
Florent Kermarrec aba8fc5c94 build/altera/quartus: allow multiple call of add_period_constraint if constraint is similar.
Similar to the changes already applied to Xilinx backend.
2020-01-09 19:45:51 +01:00
enjoy-digital e318287ec2
Merge pull request #337 from gregdavill/spi-flash
soc/cores/spi_flash: Don't tristate DQ2/DQ3 when bitbanging
2020-01-09 13:24:17 +01:00
Greg Davill 49781467d7 soc/cores/spi_flash: Don't tristate DQ2/DQ3 when bitbanging 2020-01-09 21:53:00 +10:30
Florent Kermarrec 2cf95e9f93 platforms/minispartan6: rename sd to sdcard and regroup data lines 2020-01-09 11:12:37 +01:00
Florent Kermarrec e99740e814 platforms/nexys4ddr: add sdcard pins 2020-01-09 11:00:54 +01:00
Florent Kermarrec 83ad674feb build/lattice/trellis: use a single fonction to parse device 2020-01-08 19:38:27 +01:00