Sebastien Bourdeauducq
|
7c4ca4fd66
|
dvisampler/datacapture: deserialize to 10 bits
|
2013-03-21 19:06:15 +01:00 |
|
Sebastien Bourdeauducq
|
fa2331e084
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dvisampler/clocking: generate pix reset
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2013-03-21 19:02:04 +01:00 |
|
Sebastien Bourdeauducq
|
2315544b36
|
software/videomixer: quick hack for phase detection
|
2013-03-21 15:32:26 +01:00 |
Florent Kermarrec
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db1ceccca1
|
fix uart2Csr and update miio example
|
2013-03-21 12:18:04 +01:00 |
|
Sebastien Bourdeauducq
|
a6a3d93059
|
software: add videomixer base files
|
2013-03-21 10:42:31 +01:00 |
|
Sebastien Bourdeauducq
|
bb566c9e7c
|
software/bios: change boot order
|
2013-03-21 10:41:56 +01:00 |
|
Sebastien Bourdeauducq
|
a94bf3b2c5
|
genlib/cdc/MultiReg: output clock domain defaults to sys
|
2013-03-21 10:40:02 +01:00 |
|
Sebastien Bourdeauducq
|
0a14c3714b
|
dvisampler: software controlled phase detector
|
2013-03-21 00:46:29 +01:00 |
|
Sebastien Bourdeauducq
|
b38818eb17
|
examples/sim/fir: convert to new API
|
2013-03-19 11:46:27 +01:00 |
|
Florent Kermarrec
|
24211574ec
|
update de0nano example/ remove de1 (wip)
|
2013-03-18 23:03:52 +01:00 |
|
Florent Kermarrec
|
36f3556028
|
Add uart2csr
|
2013-03-18 21:45:07 +01:00 |
|
Sebastien Bourdeauducq
|
28cb97068c
|
dvisampler/clocking: proper pix5x reset synchronization
|
2013-03-18 20:31:59 +01:00 |
|
Sebastien Bourdeauducq
|
5126f616fb
|
dvisampler: use pix5x as IODELAY clock
|
2013-03-18 19:03:17 +01:00 |
|
Sebastien Bourdeauducq
|
17f2b17654
|
fhdl/verilog: optionally disable clock domain creation
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2013-03-18 18:45:19 +01:00 |
|
Sebastien Bourdeauducq
|
797411c1a9
|
generic_platform: do not create clock domains during Verilog conversion
|
2013-03-18 18:44:58 +01:00 |
|
Sebastien Bourdeauducq
|
af4eb02551
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examples/basic/arrays: demonstrate lowering of Array in Instance expression
|
2013-03-18 18:37:23 +01:00 |
|
Sebastien Bourdeauducq
|
7a06e9457c
|
Lowering of Special expressions + support ClockSignal/ResetSignal
|
2013-03-18 18:36:50 +01:00 |
|
Sebastien Bourdeauducq
|
48aae9bee5
|
Use Instance.Input(..., ClockSignal/ResetSignal) instead of Instance.ClockPort/ResetPort
|
2013-03-18 17:44:01 +01:00 |
|
Sebastien Bourdeauducq
|
dc55289323
|
fhdl/tools/_ArrayLowerer: complete support for arrays as targets
|
2013-03-18 14:38:01 +01:00 |
|
Sebastien Bourdeauducq
|
e95d2f4779
|
fhdl/tools/value_bits_sign: support not
|
2013-03-18 09:52:43 +01:00 |
|
Sebastien Bourdeauducq
|
0c0140a8fb
|
m1crg: set CLKIN_PERIOD for vga_clock_gen
|
2013-03-17 20:16:58 +01:00 |
|
Sebastien Bourdeauducq
|
74cc045ee1
|
dvisampler/datacapture: connect IODELAY IOCLK0
|
2013-03-17 17:42:22 +01:00 |
|
Sebastien Bourdeauducq
|
621526fb7d
|
dvisampler/datacapture: fix tap counter reg
|
2013-03-17 17:36:49 +01:00 |
|
Sebastien Bourdeauducq
|
3a0cf278fd
|
dvisampler: fixes
|
2013-03-17 15:41:50 +01:00 |
|
Sebastien Bourdeauducq
|
b6fe3ace05
|
fhdl/structure: style fix
|
2013-03-17 15:33:38 +01:00 |
|
Sébastien Bourdeauducq
|
2a4cc3875c
|
Merge pull request #6 from larsclausen/master
Minor improvements
|
2013-03-17 07:33:14 -07:00 |
|
Sebastien Bourdeauducq
|
9f02ced39e
|
dvisampler: add clocking and phase detector
|
2013-03-17 14:43:10 +01:00 |
|
Sebastien Bourdeauducq
|
4bf3190244
|
MultiReg: remove idomain
|
2013-03-15 19:54:25 +01:00 |
|
Sebastien Bourdeauducq
|
0168f83523
|
MultiReg: remove idomain
|
2013-03-15 19:51:29 +01:00 |
|
Sebastien Bourdeauducq
|
2f522bdd9f
|
genlib/cdc/MultiReg: implement rename_clock_domain + get_clock_domains
|
2013-03-15 19:50:24 +01:00 |
|
Sebastien Bourdeauducq
|
e2d156ef64
|
genlib/cdc/MultiReg: remove idomain
|
2013-03-15 19:49:24 +01:00 |
|
Sebastien Bourdeauducq
|
7b49fd9386
|
fhdl/specials: fix rename_clock_domain declarations
|
2013-03-15 19:47:01 +01:00 |
|
Sebastien Bourdeauducq
|
51bec340ab
|
sim: remove PureSimulable (superseded by Module)
|
2013-03-15 19:41:30 +01:00 |
|
Sebastien Bourdeauducq
|
b2173bba9f
|
Use new ClockDomain API
|
2013-03-15 19:17:05 +01:00 |
|
Sebastien Bourdeauducq
|
dd0f3311cd
|
structure: remove Fragment.call_sim
|
2013-03-15 19:15:48 +01:00 |
|
Sebastien Bourdeauducq
|
9b9bd77d00
|
sim: compatibility with new ClockDomain API
|
2013-03-15 19:15:28 +01:00 |
|
Sebastien Bourdeauducq
|
6feb6e60b0
|
New clock_domain API
|
2013-03-15 18:46:11 +01:00 |
|
Sebastien Bourdeauducq
|
208e039bbb
|
Local clock domain example
|
2013-03-15 18:18:32 +01:00 |
|
Sebastien Bourdeauducq
|
bd8bbd9305
|
Make ClockDomains part of fragments
|
2013-03-15 18:17:33 +01:00 |
|
Sebastien Bourdeauducq
|
001beadb97
|
altera_quartus, de0nano: add copyright notices
|
2013-03-15 12:37:25 +01:00 |
|
Sebastien Bourdeauducq
|
f9e07b92a4
|
Added platform file for DE0 Nano (by Florent Kermarrec)
|
2013-03-15 11:41:38 +01:00 |
|
Sebastien Bourdeauducq
|
86d6f1d011
|
Added support for Altera Quartus (by Florent Kermarrec)
|
2013-03-15 11:32:12 +01:00 |
|
Sebastien Bourdeauducq
|
71c8172836
|
xilinx_ise/CRG_SE: reset inversion support
|
2013-03-15 11:31:36 +01:00 |
|
Sebastien Bourdeauducq
|
37d8029848
|
CRG: support reset inversion
|
2013-03-15 10:49:18 +01:00 |
|
Sebastien Bourdeauducq
|
24910173b7
|
CRG: use new Module API
|
2013-03-15 10:48:43 +01:00 |
|
Sebastien Bourdeauducq
|
5adab17efa
|
flow/actor/filter_endpoints: deterministic order
|
2013-03-14 12:20:18 +01:00 |
|
Sebastien Bourdeauducq
|
fc883198ae
|
bank/csrgen/BankArray: create banks in sorted order
|
2013-03-13 23:07:44 +01:00 |
|
Sebastien Bourdeauducq
|
2ae504fb9b
|
software/bios: default length 4 for mr command
|
2013-03-13 19:59:39 +01:00 |
|
Sebastien Bourdeauducq
|
eaef3464e9
|
Instantiate DVI sampler core for both ports
|
2013-03-13 19:56:56 +01:00 |
|
Sebastien Bourdeauducq
|
e99bafe52b
|
dvisampler: add core, EDID support
|
2013-03-13 19:56:26 +01:00 |