Florent Kermarrec
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b817cf49b3
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replace self._r_register by self._register in all CSR declaration
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2015-02-27 10:36:09 +01:00 |
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Florent Kermarrec
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e4de5a0c9d
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make.py: avoid some actions in make all (do not flash if load-bitstream is specified or if bios is in blockram)
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2015-02-27 10:23:17 +01:00 |
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Florent Kermarrec
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77a6f580e2
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gensoc: add check_cpu_memory_region and check_csr_region to detect csr and mem regions conflicts
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2015-02-27 10:23:02 +01:00 |
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Florent Kermarrec
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617bc70d7f
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liteeth: move doc
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2015-02-27 09:15:54 +01:00 |
Robert Jordens
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2b12679ef6
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add pipistrello target
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2015-02-26 21:35:42 -07:00 |
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Robert Jordens
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c9ed38dec8
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gensoc: missing self.
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2015-02-26 21:32:11 -07:00 |
Sebastien Bourdeauducq
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a3909bb5e2
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Merge branch 'master' of https://github.com/m-labs/misoc
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2015-02-26 21:28:12 -07:00 |
Yann Sionneau
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8364fe6674
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target/kc705: allow access to pll_sys signal before BUFG
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2015-02-26 15:56:10 -07:00 |
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Florent Kermarrec
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09fbbca53e
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gensoc: cpus now directly add their verilog sources
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2015-02-26 20:49:21 +01:00 |
|
Florent Kermarrec
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5e8a0c496d
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gensoc: add mem_map and mem_decoder to avoid duplications
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2015-02-26 20:12:27 +01:00 |
|
Florent Kermarrec
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5ac5ffe359
|
gensoc: get platform_id from platform
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2015-02-26 19:07:19 +01:00 |
|
Florent Kermarrec
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554731ae44
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targets/simple: make it generic (no default_platform, use platform's default_clk_name/default_clk_period)
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2015-02-26 13:08:15 +01:00 |
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Florent Kermarrec
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02b3f51382
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liteeth: fix example_designs generation
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2015-02-26 10:23:38 +01:00 |
|
Florent Kermarrec
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00862a383c
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liteeth: fix import (from liteeth --> from misoclib.liteeth)
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2015-02-26 09:48:37 +01:00 |
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Florent Kermarrec
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60effe1d95
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move files to liteeeth and create example_designs directory
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2015-02-26 09:35:14 +01:00 |
|
Sebastien Bourdeauducq
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0267868cbe
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remove litex submodule
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2015-02-25 10:40:44 -07:00 |
|
Sebastien Bourdeauducq
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658cb0e405
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merge liteeth
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2015-02-25 10:35:39 -07:00 |
|
Sebastien Bourdeauducq
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8015d12692
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move files for misoc integration
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2015-02-25 10:34:11 -07:00 |
|
Florent Kermarrec
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eef679b6d4
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phy/sim: generate sop/eop
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2015-02-25 17:47:44 +01:00 |
|
Florent Kermarrec
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6b7026f521
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add sim phy
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2015-02-24 01:42:56 +01:00 |
|
Florent Kermarrec
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282c9b9426
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test: add make.py to replace static config.py file
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2015-02-23 00:21:12 +01:00 |
|
Florent Kermarrec
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b1dee774cd
|
tty working
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2015-02-22 15:23:55 +01:00 |
|
Florent Kermarrec
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2fa28c1b5d
|
mac: add padding
|
2015-02-22 13:56:06 +01:00 |
|
Florent Kermarrec
|
acdf511bd1
|
doc: remove IP
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2015-02-21 23:33:21 +01:00 |
|
Florent Kermarrec
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65294a5577
|
add tty over udp (will need mac to insert padding)
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2015-02-21 21:26:52 +01:00 |
|
Florent Kermarrec
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0a9043b6c1
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remove MiSoC dependency
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2015-02-21 19:34:14 +01:00 |
|
Florent Kermarrec
|
6db831e5a8
|
update LiteX
|
2015-02-18 11:39:22 -07:00 |
|
Florent Kermarrec
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73ab271f9a
|
targets/kc705: fix csr address conflict on eth
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2015-02-18 10:45:18 -07:00 |
|
Florent Kermarrec
|
0a38b8c74a
|
add LiteX external core and remove ethmac
|
2015-02-18 10:43:44 -07:00 |
|
Florent Kermarrec
|
9ebb8f8022
|
remove verilog and move mxcrg.v to misoclib/mxcrg
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2015-02-18 10:40:30 -07:00 |
|
Florent Kermarrec
|
5500c41915
|
move lm32/mor1kx submodules to extcores
|
2015-02-18 10:39:18 -07:00 |
|
Florent Kermarrec
|
4c9554b65c
|
gensoc: call do_exit after SoC is built
|
2015-02-18 10:38:14 -07:00 |
|
Florent Kermarrec
|
e6f1bdb152
|
update LiteScope
|
2015-02-18 16:51:35 +01:00 |
|
Florent Kermarrec
|
e17791a85b
|
readme/make.py: add powered by Migen
|
2015-02-18 16:38:48 +01:00 |
|
Florent Kermarrec
|
70f94ea0eb
|
logo : add powered by Migen
|
2015-02-17 23:17:46 +01:00 |
|
Florent Kermarrec
|
79a7f9ecb8
|
create BaseSoC as a basic example design and build UDPSoC/EtherboneSoC on top of it
|
2015-02-17 12:37:17 +01:00 |
|
Florent Kermarrec
|
eeaf03669a
|
test: we can now test regs with Etherbone
|
2015-02-17 01:15:06 +01:00 |
|
Florent Kermarrec
|
1a3183c15d
|
etherbone: fix addressing
|
2015-02-17 00:02:49 +01:00 |
|
Florent Kermarrec
|
67958f7448
|
mac: fix missing core csr generation
|
2015-02-16 14:44:36 +01:00 |
|
Florent Kermarrec
|
da13bd536e
|
gensoc: add csr_data_width and csr_address_width as parameters In some case we want to have mode than 32 CSR or and csr_data_width != 8
|
2015-02-14 03:24:23 -08:00 |
|
Florent Kermarrec
|
3559de9b4c
|
add setup.py
|
2015-02-14 02:44:39 -08:00 |
|
Florent Kermarrec
|
aedc964908
|
update download instructions
|
2015-02-12 22:02:50 +01:00 |
|
Florent Kermarrec
|
4e4800e1b2
|
simplify litescope export with do_exit call
|
2015-02-12 21:00:45 +01:00 |
|
Florent Kermarrec
|
bceee36ef6
|
etherbone: reads OK on hardware
|
2015-02-12 15:50:07 +01:00 |
|
Florent Kermarrec
|
23c4f5c090
|
etherbone: writes OK on hardware
|
2015-02-12 13:15:30 +01:00 |
|
Florent Kermarrec
|
bfb50e698f
|
etherbone: add more debug signals
|
2015-02-12 12:33:10 +01:00 |
|
Florent Kermarrec
|
0818c29287
|
etherbone: probing OK on hardware
|
2015-02-12 12:17:17 +01:00 |
|
Florent Kermarrec
|
b6aeea676b
|
etherbone: simplify model usage
|
2015-02-12 12:09:39 +01:00 |
|
Florent Kermarrec
|
a2455b19af
|
etherbone: create example design target
|
2015-02-12 11:37:54 +01:00 |
|
Florent Kermarrec
|
f03212a30d
|
cosmetic: define params before payload
|
2015-02-12 11:10:05 +01:00 |