Sebastien Bourdeauducq
|
24877f271b
|
actorlib/spi: fix memory port we/wd
|
2012-10-04 20:10:24 +02:00 |
|
Sebastien Bourdeauducq
|
035870703f
|
flow/actorlib: Simple Processor Interface (WIP)
|
2012-10-04 18:22:22 +02:00 |
|
Sebastien Bourdeauducq
|
8101b68965
|
fhdl: fix instance get_io
|
2012-09-28 18:02:03 +02:00 |
|
Sebastien Bourdeauducq
|
c273866b08
|
fhdl: support expressions in instance ports
|
2012-09-22 20:51:10 +02:00 |
|
Sebastien Bourdeauducq
|
2fc9cae88a
|
fhdl: support inverted clock ports in instances
|
2012-09-22 20:50:49 +02:00 |
|
Sebastien Bourdeauducq
|
2e14569b5c
|
fhdl/verilog: sort clock domains by name
|
2012-09-11 10:00:03 +02:00 |
|
Sebastien Bourdeauducq
|
9a18a9df3f
|
fhdl: list signals in execution order
|
2012-09-11 09:59:37 +02:00 |
|
Sebastien Bourdeauducq
|
e16353a281
|
Multi-clock design support + new instance API
|
2012-09-10 23:45:02 +02:00 |
|
Sébastien Bourdeauducq
|
6490785b6c
|
Merge pull request #3 from brandonhamilton/upstream
Optionally accept iverilog simulator options
|
2012-09-09 10:52:52 -07:00 |
|
Sebastien Bourdeauducq
|
b45c9546eb
|
fhdl/namer: better handling of indices
|
2012-09-09 19:33:55 +02:00 |
|
Sebastien Bourdeauducq
|
589251fffd
|
fhdl/tracer: support BUILD_LIST opcode
|
2012-09-09 18:53:24 +02:00 |
|
Sebastien Bourdeauducq
|
910c350021
|
fhdl/namer: use execution order indices for variable names as well
|
2012-09-09 17:31:35 +02:00 |
|
Sebastien Bourdeauducq
|
f3e3a3eec7
|
fhdl/namer: number objects according to execution order
|
2012-09-09 12:27:32 +02:00 |
|
Sebastien Bourdeauducq
|
51f9a2a963
|
fhdl/namer: simplify + more relevant names
|
2012-09-09 01:26:33 +02:00 |
|
Sebastien Bourdeauducq
|
4164fb4ac9
|
bus/csr: configurable data width
|
2012-08-26 21:19:34 +02:00 |
|
Sebastien Bourdeauducq
|
5bf19c155f
|
sim: ensure clean IPC shutdown
|
2012-08-05 00:16:11 +02:00 |
|
Sebastien Bourdeauducq
|
47c341ecdf
|
flow/isd: add freeze register
|
2012-08-04 23:39:52 +02:00 |
|
Sebastien Bourdeauducq
|
6de517f59c
|
flow/network: remove print
|
2012-08-03 18:50:57 +02:00 |
|
Sebastien Bourdeauducq
|
25cb25a8ae
|
flow/network: option to add debugger
|
2012-08-03 18:49:35 +02:00 |
|
Sebastien Bourdeauducq
|
fd0e281dfc
|
flow: in-system debugger module
|
2012-08-03 18:49:04 +02:00 |
|
Sebastien Bourdeauducq
|
adacdadd58
|
flow/hooks/DFGHook: add iterator on hooks
|
2012-08-03 18:48:35 +02:00 |
|
Sebastien Bourdeauducq
|
37fe6d64c3
|
flow: EndpointHook -> EndpointSimHook
|
2012-08-03 12:58:41 +02:00 |
|
Sebastien Bourdeauducq
|
30f1e77c18
|
corelogic/ReorderBuffer: do not touch empty count when issuing and reading at the same time
|
2012-07-13 20:21:04 +02:00 |
|
Sebastien Bourdeauducq
|
8de192dfbd
|
x.bv.width -> len(x)
|
2012-07-13 18:32:54 +02:00 |
|
Sebastien Bourdeauducq
|
9cdc88eadf
|
fhdl: len() for Constant
|
2012-07-13 18:16:50 +02:00 |
|
Sebastien Bourdeauducq
|
8c169a99df
|
corelogic/misc: remove multimux
|
2012-07-13 18:05:57 +02:00 |
|
Sebastien Bourdeauducq
|
599ed8d470
|
fhdl: fix value_bv for operators
|
2012-07-13 17:40:49 +02:00 |
|
Sebastien Bourdeauducq
|
b4613d913f
|
bus/wishbone: remove use of deprecated multimux
|
2012-07-13 17:17:20 +02:00 |
|
Sebastien Bourdeauducq
|
7f47a2568a
|
fhdl: remove _StatementList
|
2012-07-13 17:07:56 +02:00 |
|
Sebastien Bourdeauducq
|
8062e48697
|
bus/asmibus: fix per-port tag generation
|
2012-07-12 19:37:50 +02:00 |
|
Sebastien Bourdeauducq
|
c543edf6f3
|
actorlib/dma_asmi: out-of-order reader and class factory
|
2012-07-12 18:34:13 +02:00 |
|
Sebastien Bourdeauducq
|
43653dbe1a
|
corelogic: reorder buffer (untested)
|
2012-07-12 18:33:28 +02:00 |
|
Sebastien Bourdeauducq
|
eed8fa374d
|
fhdl/arrays: use correct BV for intermediate signals
|
2012-07-11 12:06:32 +02:00 |
|
Sebastien Bourdeauducq
|
ed27783a53
|
fhdl: arrays (TODO: use correct BV for intermediate signals)
|
2012-07-09 15:16:38 +02:00 |
|
Sebastien Bourdeauducq
|
c82a468506
|
bus: CSR initiator
|
2012-07-07 22:36:15 +02:00 |
|
Sebastien Bourdeauducq
|
0b19112f8f
|
actorlib/misc/IntSequence: add offset feature
|
2012-07-07 00:10:23 +02:00 |
|
Sebastien Bourdeauducq
|
518501c493
|
flow/perftools: refactor to use hooks
|
2012-07-06 23:36:23 +02:00 |
|
Sebastien Bourdeauducq
|
6cf38bfcba
|
flow: hooks
|
2012-07-06 23:36:10 +02:00 |
|
Sebastien Bourdeauducq
|
a49dcb328a
|
actorlib/structuring/Cast: rawbits parameter
|
2012-06-29 16:10:50 +02:00 |
|
Sebastien Bourdeauducq
|
fa5a9915c3
|
doc: actor network
|
2012-06-25 16:07:45 +02:00 |
|
Sebastien Bourdeauducq
|
920aa5dc60
|
actorlib: merge composer into ala + derive ComposableSource from ActorNode
|
2012-06-25 11:34:58 +02:00 |
|
Sebastien Bourdeauducq
|
bbfa120e2f
|
doc: arithmetic and logic actors
|
2012-06-24 19:56:31 +02:00 |
|
Sebastien Bourdeauducq
|
fd233d5b3c
|
Move arithmetic actors to actorlib
|
2012-06-24 19:13:49 +02:00 |
|
Sebastien Bourdeauducq
|
1edaec0d75
|
control.For -> misc.IntSequence
|
2012-06-22 15:01:47 +02:00 |
|
Sebastien Bourdeauducq
|
4785ca526b
|
flow/perftool: fix cpt equation
|
2012-06-21 00:41:22 +02:00 |
|
Sebastien Bourdeauducq
|
cbc387f69e
|
actorlib/sim/SimActor: remove dead time between transactions
|
2012-06-20 22:39:52 +02:00 |
|
Sebastien Bourdeauducq
|
6aff41a883
|
actorlib/structuring/Pack: drive busy signal
|
2012-06-20 22:39:03 +02:00 |
|
Sebastien Bourdeauducq
|
34d8ae3c11
|
flow: perftools
|
2012-06-20 21:59:17 +02:00 |
|
Sebastien Bourdeauducq
|
6fac3f027f
|
examples/dataflow: structuring test
|
2012-06-20 18:25:01 +02:00 |
|
Sebastien Bourdeauducq
|
7d0e179a03
|
actorlib: structuring (untested)
|
2012-06-20 16:35:01 +02:00 |
|
Sebastien Bourdeauducq
|
1576cb0950
|
actorlib/control: simplify + fix
|
2012-06-17 21:19:47 +02:00 |
|
Sebastien Bourdeauducq
|
66ac62d0bb
|
flow/network: fix handling of edges with subrecords at both ends
|
2012-06-17 18:31:45 +02:00 |
|
Sebastien Bourdeauducq
|
75d569a12c
|
actorlib/control: use numbers of bits instead of maxima
|
2012-06-17 18:29:57 +02:00 |
|
Sebastien Bourdeauducq
|
4873cfe1a7
|
flow/plumbing: Combinator/Splitter should not inherit CombinatorialActor
|
2012-06-17 13:45:18 +02:00 |
|
Sebastien Bourdeauducq
|
98c9da95d1
|
flow/network: handle default endpoints correctly in _infer_plumbing_layout
|
2012-06-16 22:41:15 +02:00 |
|
Sebastien Bourdeauducq
|
9af87367eb
|
flow/network: require ActorNode be passed to add_connection
|
2012-06-16 22:40:26 +02:00 |
|
Sebastien Bourdeauducq
|
b0b0380ea7
|
flow/network: fix ActorNode default params
|
2012-06-16 22:39:31 +02:00 |
|
Sebastien Bourdeauducq
|
1a576e5c83
|
flow/actor: fix busy signal generation for pipelined actors
|
2012-06-16 22:38:45 +02:00 |
|
Sebastien Bourdeauducq
|
9228e8a96d
|
flow/actor: add single_sink/single_source retrieval methods
|
2012-06-16 22:38:16 +02:00 |
|
Sebastien Bourdeauducq
|
c1450daa93
|
flow: insert splitters
|
2012-06-16 21:23:42 +02:00 |
|
Sebastien Bourdeauducq
|
bde8361e19
|
flow: insert combinators and infer plumbing layout
|
2012-06-16 17:30:54 +02:00 |
|
Sebastien Bourdeauducq
|
da522cd58d
|
Abstract actor graphs
|
2012-06-15 17:52:19 +02:00 |
|
Sebastien Bourdeauducq
|
b14be4c8a3
|
actorlib: ASMI sequential reader
|
2012-06-12 21:04:47 +02:00 |
|
Sebastien Bourdeauducq
|
ce9e35b8ef
|
fix SimActor get_fragment
|
2012-06-12 17:52:08 +02:00 |
|
Sebastien Bourdeauducq
|
8a23451237
|
PureSimulable
|
2012-06-12 17:08:56 +02:00 |
|
Sebastien Bourdeauducq
|
a591510189
|
ASMI simulation models
|
2012-06-12 16:57:00 +02:00 |
|
Sebastien Bourdeauducq
|
b7a84b3750
|
wishbone: base TargetModel class
|
2012-06-10 17:05:10 +02:00 |
|
Sebastien Bourdeauducq
|
ec501e7797
|
bus/wishbone: target model
|
2012-06-10 16:40:33 +02:00 |
|
Sebastien Bourdeauducq
|
f061b25a24
|
bus/wishbone/Tap: remove ack feature
|
2012-06-10 12:46:24 +02:00 |
|
Sebastien Bourdeauducq
|
009f26bb9d
|
flow/network: refactor graph
|
2012-06-08 22:49:49 +02:00 |
|
Sebastien Bourdeauducq
|
de408b2cba
|
flow/ala: fix typo
|
2012-06-08 22:48:47 +02:00 |
|
Sebastien Bourdeauducq
|
356051e8a8
|
actorlib: WB reader simulation OK
|
2012-06-08 21:31:05 +02:00 |
|
Sebastien Bourdeauducq
|
11674242c4
|
Use super() instead of calling parent constructors directly
|
2012-06-08 18:06:12 +02:00 |
|
Sebastien Bourdeauducq
|
152a7e282e
|
actorlib/sim: use set instead of list to represent active transactions
|
2012-06-08 17:56:52 +02:00 |
|
Sebastien Bourdeauducq
|
910c7806cf
|
actorlib: generator-based generic simulation actor
|
2012-06-08 17:54:03 +02:00 |
|
Sebastien Bourdeauducq
|
b145f9e5e2
|
sim: multiread/multiwrite
|
2012-06-08 17:52:32 +02:00 |
|
Sebastien Bourdeauducq
|
f38ef626de
|
corelogic/record: better repr
|
2012-06-08 17:49:31 +02:00 |
|
Sebastien Bourdeauducq
|
1c0f636c8d
|
flow: generic parameter passing to Actor from sequential/pipelined
|
2012-06-07 18:24:33 +02:00 |
|
Sebastien Bourdeauducq
|
a1fc86af8f
|
flow: fix actor repr
|
2012-06-07 15:48:35 +02:00 |
|
Sebastien Bourdeauducq
|
680a34465d
|
flow: refactor scheduling models
|
2012-06-07 14:44:43 +02:00 |
|
Sebastien Bourdeauducq
|
493b181af1
|
bank/description: pad unaligned multi-word registers at the top
|
2012-05-21 22:55:23 +02:00 |
|
Sebastien Bourdeauducq
|
9449bbea0a
|
Add LICENSE file
|
2012-05-21 19:56:23 +02:00 |
|
Sebastien Bourdeauducq
|
68cd445662
|
bus/wishbone2asmi: fix cache tag size
|
2012-05-15 15:18:03 +02:00 |
|
Sebastien Bourdeauducq
|
0bea1e2589
|
asmi: dat_wm high to disable data write
|
2012-05-15 14:41:54 +02:00 |
|
Sebastien Bourdeauducq
|
f2c20e4af0
|
bus/asmibus/hub: hack to prevent comb loops
|
2012-04-30 17:11:42 -05:00 |
|
Sebastien Bourdeauducq
|
398ece8fe2
|
fhdl/verilog: add option to display which comb blocks are run
This is a debug hack to help find combinatorial loops in designs.
|
2012-04-30 16:38:40 -05:00 |
|
Sebastien Bourdeauducq
|
0b62e573ae
|
sim: pass extra keyword arguments to Verilog converter
|
2012-04-30 16:38:17 -05:00 |
|
Sebastien Bourdeauducq
|
6a52e44d09
|
fhdl: support len() on signals
|
2012-04-08 18:06:22 +02:00 |
|
Sebastien Bourdeauducq
|
b9c533be51
|
bank/csrgen: allow specifying existing CSR interface
|
2012-04-06 14:59:09 +02:00 |
Brandon Hamilton
|
49b58a03a0
|
Optionally accept iverilog simulator options
|
2012-04-03 12:58:19 +02:00 |
|
Sebastien Bourdeauducq
|
2a4e49e381
|
fhdl: phase out pads
|
2012-04-02 19:21:43 +02:00 |
|
Sebastien Bourdeauducq
|
623e8e436a
|
fhdl/verilog: do not attempt to initialize instance and mem output signals
|
2012-04-02 12:59:42 +02:00 |
|
Sebastien Bourdeauducq
|
6e3b25ebb6
|
bus/dfi: reset active low signals to 1
|
2012-04-01 17:43:24 +02:00 |
|
Sebastien Bourdeauducq
|
d3c6b8d16f
|
sim/proxy: support lists
|
2012-04-01 17:19:53 +02:00 |
|
Sebastien Bourdeauducq
|
f3ae22f488
|
fhdl/verilog: initialize internal read-only signals with their reset values
|
2012-04-01 16:39:11 +02:00 |
|
Sebastien Bourdeauducq
|
0dfc215fe8
|
corelogic/roundrobin: handle correctly special case with 1 request source
|
2012-03-31 18:01:40 +02:00 |
|
Sebastien Bourdeauducq
|
94b02aa8ed
|
bus/asmicon: initiator
|
2012-03-30 22:16:31 +02:00 |
|
Sebastien Bourdeauducq
|
bb864c65dc
|
sim: proxy
|
2012-03-30 16:40:26 +02:00 |
|
Sebastien Bourdeauducq
|
081b658e2d
|
Update copyright notices
|
2012-03-23 16:41:30 +01:00 |
|
Sebastien Bourdeauducq
|
d47b564fad
|
corelogic/fsm: typo
|
2012-03-18 22:12:46 +01:00 |