Hardware
/
litex
mirror of https://github.com/enjoy-digital/litex.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity
415 Commits 40 Branches 14 Tags 26 MiB
Commit Graph

332 Commits

Author SHA1 Message Date
Sebastien Bourdeauducq 1576cb0950 actorlib/control: simplify + fix 2012-06-17 21:19:47 +02:00
Sebastien Bourdeauducq 66ac62d0bb flow/network: fix handling of edges with subrecords at both ends 2012-06-17 18:31:45 +02:00
Sebastien Bourdeauducq 75d569a12c actorlib/control: use numbers of bits instead of maxima 2012-06-17 18:29:57 +02:00
Sebastien Bourdeauducq 4873cfe1a7 flow/plumbing: Combinator/Splitter should not inherit CombinatorialActor 2012-06-17 13:45:18 +02:00
Sebastien Bourdeauducq 98c9da95d1 flow/network: handle default endpoints correctly in _infer_plumbing_layout 2012-06-16 22:41:15 +02:00
Sebastien Bourdeauducq 9af87367eb flow/network: require ActorNode be passed to add_connection 2012-06-16 22:40:26 +02:00
Sebastien Bourdeauducq b0b0380ea7 flow/network: fix ActorNode default params 2012-06-16 22:39:31 +02:00
Sebastien Bourdeauducq 1a576e5c83 flow/actor: fix busy signal generation for pipelined actors 2012-06-16 22:38:45 +02:00
Sebastien Bourdeauducq 9228e8a96d flow/actor: add single_sink/single_source retrieval methods 2012-06-16 22:38:16 +02:00
Sebastien Bourdeauducq c1450daa93 flow: insert splitters 2012-06-16 21:23:42 +02:00
Sebastien Bourdeauducq bde8361e19 flow: insert combinators and infer plumbing layout 2012-06-16 17:30:54 +02:00
Sebastien Bourdeauducq da522cd58d Abstract actor graphs 2012-06-15 17:52:19 +02:00
Sebastien Bourdeauducq b14be4c8a3 actorlib: ASMI sequential reader 2012-06-12 21:04:47 +02:00
Sebastien Bourdeauducq ce9e35b8ef fix SimActor get_fragment 2012-06-12 17:52:08 +02:00
Sebastien Bourdeauducq 8a23451237 PureSimulable 2012-06-12 17:08:56 +02:00
Sebastien Bourdeauducq a591510189 ASMI simulation models 2012-06-12 16:57:00 +02:00
Sebastien Bourdeauducq b7a84b3750 wishbone: base TargetModel class 2012-06-10 17:05:10 +02:00
Sebastien Bourdeauducq ec501e7797 bus/wishbone: target model 2012-06-10 16:40:33 +02:00
Sebastien Bourdeauducq f061b25a24 bus/wishbone/Tap: remove ack feature 2012-06-10 12:46:24 +02:00
Sebastien Bourdeauducq 009f26bb9d flow/network: refactor graph 2012-06-08 22:49:49 +02:00
Sebastien Bourdeauducq de408b2cba flow/ala: fix typo 2012-06-08 22:48:47 +02:00
Sebastien Bourdeauducq 356051e8a8 actorlib: WB reader simulation OK 2012-06-08 21:31:05 +02:00
Sebastien Bourdeauducq 11674242c4 Use super() instead of calling parent constructors directly 2012-06-08 18:06:12 +02:00
Sebastien Bourdeauducq 152a7e282e actorlib/sim: use set instead of list to represent active transactions 2012-06-08 17:56:52 +02:00
Sebastien Bourdeauducq 910c7806cf actorlib: generator-based generic simulation actor 2012-06-08 17:54:03 +02:00
Sebastien Bourdeauducq b145f9e5e2 sim: multiread/multiwrite 2012-06-08 17:52:32 +02:00
Sebastien Bourdeauducq f38ef626de corelogic/record: better repr 2012-06-08 17:49:31 +02:00
Sebastien Bourdeauducq 1c0f636c8d flow: generic parameter passing to Actor from sequential/pipelined 2012-06-07 18:24:33 +02:00
Sebastien Bourdeauducq a1fc86af8f flow: fix actor repr 2012-06-07 15:48:35 +02:00
Sebastien Bourdeauducq 680a34465d flow: refactor scheduling models 2012-06-07 14:44:43 +02:00
Sebastien Bourdeauducq 493b181af1 bank/description: pad unaligned multi-word registers at the top 2012-05-21 22:55:23 +02:00
Sebastien Bourdeauducq 9449bbea0a Add LICENSE file 2012-05-21 19:56:23 +02:00
Sebastien Bourdeauducq 68cd445662 bus/wishbone2asmi: fix cache tag size 2012-05-15 15:18:03 +02:00
Sebastien Bourdeauducq 0bea1e2589 asmi: dat_wm high to disable data write 2012-05-15 14:41:54 +02:00
Sebastien Bourdeauducq f2c20e4af0 bus/asmibus/hub: hack to prevent comb loops 2012-04-30 17:11:42 -05:00
Sebastien Bourdeauducq 398ece8fe2 fhdl/verilog: add option to display which comb blocks are run 
This is a debug hack to help find combinatorial loops in designs.
 2012-04-30 16:38:40 -05:00
Sebastien Bourdeauducq 0b62e573ae sim: pass extra keyword arguments to Verilog converter 2012-04-30 16:38:17 -05:00
Sebastien Bourdeauducq 6a52e44d09 fhdl: support len() on signals 2012-04-08 18:06:22 +02:00
Sebastien Bourdeauducq b9c533be51 bank/csrgen: allow specifying existing CSR interface 2012-04-06 14:59:09 +02:00
Brandon Hamilton 49b58a03a0 Optionally accept iverilog simulator options 2012-04-03 12:58:19 +02:00
Sebastien Bourdeauducq 2a4e49e381 fhdl: phase out pads 2012-04-02 19:21:43 +02:00
Sebastien Bourdeauducq 623e8e436a fhdl/verilog: do not attempt to initialize instance and mem output signals 2012-04-02 12:59:42 +02:00
Sebastien Bourdeauducq 6e3b25ebb6 bus/dfi: reset active low signals to 1 2012-04-01 17:43:24 +02:00
Sebastien Bourdeauducq d3c6b8d16f sim/proxy: support lists 2012-04-01 17:19:53 +02:00
Sebastien Bourdeauducq f3ae22f488 fhdl/verilog: initialize internal read-only signals with their reset values 2012-04-01 16:39:11 +02:00
Sebastien Bourdeauducq 0dfc215fe8 corelogic/roundrobin: handle correctly special case with 1 request source 2012-03-31 18:01:40 +02:00
Sebastien Bourdeauducq 94b02aa8ed bus/asmicon: initiator 2012-03-30 22:16:31 +02:00
Sebastien Bourdeauducq bb864c65dc sim: proxy 2012-03-30 16:40:26 +02:00
Sebastien Bourdeauducq 081b658e2d Update copyright notices 2012-03-23 16:41:30 +01:00
Sebastien Bourdeauducq d47b564fad corelogic/fsm: typo 2012-03-18 22:12:46 +01:00
Sebastien Bourdeauducq 5f28103769 corelogic/fsm: delayed enters 2012-03-18 00:09:40 +01:00
Sebastien Bourdeauducq a4294762d0 corelogic/roundrobin: CE switching 2012-03-16 16:54:47 +01:00
Sebastien Bourdeauducq e969b9afc3 corelogic: convert timeline to function and move to misc 2012-03-15 20:25:44 +01:00
Sebastien Bourdeauducq 1665f293a6 bus/asmibus/hub: require finalization before get_slots 2012-03-14 16:19:29 +01:00
Sebastien Bourdeauducq 5c0cc6292c fhdl: export log2_int 2012-03-14 12:19:42 +01:00
Sebastien Bourdeauducq bfcd4e636b fhdl: handle negative constants correctly 2012-03-08 20:49:24 +01:00
Sebastien Bourdeauducq ab800fa2ed bus: generic transaction model 2012-03-08 18:14:06 +01:00
Sebastien Bourdeauducq 678a89d572 sim: fix zero encoding 2012-03-08 15:34:08 +01:00
Sebastien Bourdeauducq decbd069fa sim: fix message debug formatting 2012-03-08 15:27:35 +01:00
Sebastien Bourdeauducq 98e96b3952 sim: make initialization cycle optional (selectable by function attribute) 2012-03-06 19:43:59 +01:00
Sebastien Bourdeauducq 8160ced2e9 sim: memory access 2012-03-06 19:29:39 +01:00
Sebastien Bourdeauducq db8f8bf2e3 fhdl: register memory objects with namespace 2012-03-06 18:33:44 +01:00
Sebastien Bourdeauducq 6f829c7afc sim: support for signed numbers 2012-03-06 16:46:18 +01:00
Sebastien Bourdeauducq 90184b22d2 fhdl/verilog: fix signed constant conversion 2012-03-06 16:45:44 +01:00
Sebastien Bourdeauducq 9da512dbf5 sim: VCD generation 2012-03-06 15:26:04 +01:00
Sebastien Bourdeauducq 22b3c11b93 sim: clean startup/shutdown 2012-03-06 15:00:02 +01:00
Sebastien Bourdeauducq 06de17b16c sim: remove temporary files and socket 2012-03-06 14:20:26 +01:00
Sebastien Bourdeauducq 7230508e7c fhdl/namer: do not reference objects with __del__ methods to avoid uncollectable cycles 2012-03-06 14:18:22 +01:00
Sebastien Bourdeauducq 2c375e900f sim: remove default sockaddr 2012-03-06 13:58:49 +01:00
Sebastien Bourdeauducq 8d16fde48c fhdl: add simulation functions in fragment 2012-03-06 13:58:22 +01:00
Sebastien Bourdeauducq aac9752558 sim: basic functionality working 2012-03-05 20:31:41 +01:00
Sebastien Bourdeauducq 29859acc34 sim: two way IPC working 2012-03-04 19:17:03 +01:00
Sebastien Bourdeauducq 8586daf2dd sim: IPC module (lacks str/int encoding) 2012-03-03 18:55:38 +01:00
Sebastien Bourdeauducq 1b8cb5b46c bus/dfi: fix multiphase naming 2012-02-19 17:57:04 +01:00
Sebastien Bourdeauducq d8d4e81b6e bank/csrgen: fix RE generation 2012-02-18 18:56:18 +01:00
Sebastien Bourdeauducq 55a265d967 bank: add RE signal for registers made of fields 2012-02-17 23:52:06 +01:00
Sebastien Bourdeauducq 92dfbb92dd bus: add interconnect statements function 2012-02-17 23:51:32 +01:00
Sebastien Bourdeauducq f995e8b92e fhdl: check we pass BV to signals 2012-02-17 23:50:54 +01:00
Sebastien Bourdeauducq a1ad30faab fhdl/verilog: properly connect instance inouts 2012-02-17 11:08:41 +01:00
Sebastien Bourdeauducq ca7056b07f fhdl: support forwarding of bidirectional signals from instance ports 2012-02-16 18:34:32 +01:00
Sebastien Bourdeauducq c08687b9c6 bus/dfi: filter signals by direction 2012-02-15 21:48:05 +01:00
Sebastien Bourdeauducq ef7aea0f31 bank: omit device write register when access_bus==READ_ONLY and access_dev==WRITE_ONLY 2012-02-15 18:23:31 +01:00
Sebastien Bourdeauducq fa9cf3e466 bus: add DFI 2012-02-15 18:09:14 +01:00
Sebastien Bourdeauducq 91e279ee04 bank/csrgen: use new bus API 2012-02-15 16:42:17 +01:00
Sebastien Bourdeauducq af5230c8ee bus: fix simple interconnect 2012-02-15 16:42:05 +01:00
Sebastien Bourdeauducq 0493212124 bus: simplify and cleanup 
Unify slave and master interfaces
Remove signal direction suffixes
Generic simple interconnect
Wishbone point-to-point interconnect
Description filter (get_name)
Misc cleanups
 2012-02-15 16:30:16 +01:00
Sebastien Bourdeauducq 46b1f74e98 bus/asmibus/hub: forward data and tag_call 2012-02-14 14:00:17 +01:00
Sebastien Bourdeauducq 0c214b484e Use double quotes for all strings 2012-02-14 13:12:43 +01:00
Sebastien Bourdeauducq e11d9b9322 bus/wishbone2asmi: cache hits working 2012-02-13 23:11:16 +01:00
Sebastien Bourdeauducq 1662e1b3bc corelogic: support reverse in displacer/chooser 2012-02-13 23:10:27 +01:00
Sebastien Bourdeauducq 264be80f2d Fix syntax errors and other stupid problems 2012-02-13 22:28:02 +01:00
Sebastien Bourdeauducq 8a61d9d121 bus/csr: Rename a->adr d->dat to be consistent with the other buses 2012-02-13 21:46:39 +01:00
Sebastien Bourdeauducq 060426cb59 bus/wishbone2asmi: set WM, and send 0 when inactive 2012-02-13 16:49:43 +01:00
Sebastien Bourdeauducq cad9d3b960 bus: Wishbone to ASMI caching bridge (untested) 2012-02-13 16:29:38 +01:00
Sebastien Bourdeauducq 244bf17db7 corelogic/misc: displacer + chooser 2012-02-11 20:57:08 +01:00
Sebastien Bourdeauducq e10e4360f3 corelogic/misc/multimux: less confusing variable name 2012-02-11 20:56:51 +01:00
Sebastien Bourdeauducq 7894411418 bus/asmibus: fix typo 2012-02-11 20:56:01 +01:00
Sebastien Bourdeauducq 28b0c340af corelogic/record: add to_signal convenience function 2012-02-11 20:55:23 +01:00
Sebastien Bourdeauducq e62ac1d3a1 corelogic/misc: contiguous split 2012-02-11 11:52:15 +01:00
Sebastien Bourdeauducq ef436a1ec9 bus/asmibus: add get_slots, fix get_fragment 2012-02-10 17:49:06 +01:00
Sebastien Bourdeauducq 945d655d45 bus: ASMI hub (untested) 2012-02-10 15:21:04 +01:00
Sebastien Bourdeauducq 47883675db bus/wishbone2csr: truncate WB data 2012-02-06 18:43:34 +01:00
Sebastien Bourdeauducq 1eb348c573 fhdl: do not attempt slicing non-array signals to keep Verilog happy 2012-02-06 18:07:02 +01:00
Sebastien Bourdeauducq fcd6583cbb bank: event manager 2012-02-06 17:39:32 +01:00
Sebastien Bourdeauducq 3a2a0c4dd8 bank: support registers larger than the bus word width 2012-02-06 16:15:27 +01:00
Sebastien Bourdeauducq f3ddfffc47 bank: refactoring 2012-02-06 13:55:50 +01:00
Sebastien Bourdeauducq 1a86f26a66 bank/csrgen: use enumerate 2012-02-06 11:18:30 +01:00
Sebastien Bourdeauducq 629e771fc0 fhdl/structure: binary constant builder 2012-02-05 19:32:11 +01:00
Lars-Peter Clausen 8380318e84 Use enumerate(x) instead of zip(range(x), x) 
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
 2012-02-02 21:28:00 +01:00
Lars-Peter Clausen 2b3f00cbc1 fhdl/namer: Add support for STORE_DEREF opcode 
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
 2012-02-02 21:15:10 +01:00
Sebastien Bourdeauducq 6a9b59786b fhdl/namer: extract variable names with bytecode inspection 2012-01-28 23:17:44 +01:00
Sebastien Bourdeauducq 5c2df45577 fhdl: do not prefix instance signal names 2012-01-28 11:39:28 +01:00
Sebastien Bourdeauducq a99c2acfa8 Remove explicit bus names and rely on the new automatic namer 2012-01-27 22:20:57 +01:00
Sebastien Bourdeauducq 685b5eb08f fhdl: support memory read enable 2012-01-27 21:39:23 +01:00
Sebastien Bourdeauducq 0cc7e2ac1e fhdl: make WRITE_FIRST default 2012-01-27 21:35:58 +01:00
Sebastien Bourdeauducq 5405a83ff9 fhdl: memories working 2012-01-27 20:22:17 +01:00
Sebastien Bourdeauducq a5bd111370 fhdl/verilog: clean up signal classification and support memory descriptions 2012-01-27 16:54:48 +01:00
Sebastien Bourdeauducq 6b1d775e9f fhdl/structure: memory description 2012-01-27 16:53:34 +01:00
Sebastien Bourdeauducq 1966117e17 flow/ala: fix typo for And (thanks Lars) 2012-01-22 00:32:02 +01:00
Sebastien Bourdeauducq 076c171c7b Use meaningful class names 2012-01-20 23:07:32 +01:00
Sebastien Bourdeauducq d3d5b481fe Include fragment pads in pre-naming dictionary 2012-01-20 22:59:40 +01:00
Sebastien Bourdeauducq 039c6d8eb4 namer/trace_back: behave on None code_context 2012-01-20 22:52:50 +01:00
Sebastien Bourdeauducq e9be3241f6 Fix instance support 2012-01-20 22:36:17 +01:00
Sebastien Bourdeauducq e4f531a739 Include unused I/Os in pre-naming dictionary and register signals with name_override 2012-01-20 22:20:32 +01:00
Sebastien Bourdeauducq 904d14d4cf Remove NoContext 2012-01-20 22:15:44 +01:00
Sebastien Bourdeauducq 05b20d4987 Only include context prefix when necessary 2012-01-19 19:25:04 +01:00
Sebastien Bourdeauducq fc473e31eb Fix disjoint namespace test 2012-01-19 19:24:43 +01:00
Sebastien Bourdeauducq 00d3eb7989 Always include last step in names 2012-01-19 18:42:43 +01:00
Sebastien Bourdeauducq 4eac60d181 New naming system: second attempt 2012-01-19 18:25:25 +01:00
Sebastien Bourdeauducq 4c85d921b3 corelogic/record: empty default name 2012-01-16 19:38:14 +01:00
Sebastien Bourdeauducq bdde97f5fd New naming system beginning to work 2012-01-16 18:42:55 +01:00
Sebastien Bourdeauducq ab8e08a2ed fhdl: new naming system (broken) 2012-01-16 18:09:52 +01:00
Sebastien Bourdeauducq e6bfad498d actorlib/control: 'for' generator 2012-01-15 22:08:33 +01:00
Sebastien Bourdeauducq c3d7b98b43 dma_wishbone: small syntax simplification thanks to None statements 2012-01-15 17:46:15 +01:00
Sebastien Bourdeauducq aa8b8da684 fhdl: allow None statements 2012-01-15 17:45:54 +01:00
Sebastien Bourdeauducq 85491efc68 wishbone_dma: convert to new endpoint API and fix some bugs 2012-01-15 16:41:15 +01:00
Sebastien Bourdeauducq 77b3c8e3bb bus: list signals 2012-01-15 15:48:51 +01:00
Sebastien Bourdeauducq 3c7161cc34 flow: saner endpoint management 2012-01-15 15:09:44 +01:00
Sebastien Bourdeauducq 20425703fa Wishbone: omit fixed LSBs 2012-01-13 17:29:05 +01:00
Sebastien Bourdeauducq 077fd9fdbc actorlib: Wishbone DMA read master (WIP) 2012-01-10 17:10:18 +01:00
Sebastien Bourdeauducq c93eb5f482 record: return offset 2012-01-10 17:10:03 +01:00
Sebastien Bourdeauducq a6e5f3e766 flow: simplify actor fragment interface 2012-01-10 15:54:51 +01:00
Sebastien Bourdeauducq 683e6b4a6c record: support aligned flattening 2012-01-09 19:16:11 +01:00
Sebastien Bourdeauducq b06e70d849 corelogic: FSM 2012-01-09 16:28:48 +01:00
Sebastien Bourdeauducq 47ae303846 record: cleanup 2012-01-09 15:20:09 +01:00
Sebastien Bourdeauducq cef1c5d3af record: better exception code 2012-01-09 15:17:24 +01:00
Sebastien Bourdeauducq 89bf704b2b record: preserve order 2012-01-09 15:14:42 +01:00
Sebastien Bourdeauducq bdcaeb159b flow: draw network graph 2012-01-09 14:21:54 +01:00
Sebastien Bourdeauducq d26ded93d8 flow: actor busy signal 2012-01-09 14:21:45 +01:00
Sebastien Bourdeauducq d2d55372d8 Composer (WIP) 2012-01-08 13:56:11 +01:00