Sebastien Bourdeauducq
156ef43ace
genlib/cdc: add NoRetiming
2013-04-25 14:56:45 +02:00
Sebastien Bourdeauducq
b862b070d6
fhdl/verilog: recursive Special lowering
2013-04-25 14:56:26 +02:00
Sebastien Bourdeauducq
67c3119249
genlib/fifo: add asynchronous FIFO
2013-04-25 13:30:37 +02:00
Sebastien Bourdeauducq
fee228a09f
fhdl/specials/memory: do not write address register for async reads
2013-04-25 13:30:05 +02:00
Sebastien Bourdeauducq
6c08cd67aa
graycounter: expose binary output
2013-04-25 13:11:15 +02:00
Sebastien Bourdeauducq
0f9df2d732
genlib: add Gray counter
2013-04-24 19:13:36 +02:00
Florent Kermarrec
f599fe4ade
Support for resetless clock domains
2013-04-23 11:54:05 +02:00
Sebastien Bourdeauducq
bd0ae6592e
Add setup.py
2013-04-19 14:04:59 +02:00
Sebastien Bourdeauducq
6204bcfa10
README: fix quick intro
2013-04-19 14:00:46 +02:00
Sebastien Bourdeauducq
29eaf068f3
xilinx_ise: do not attempt to source settings file on Windows
2013-04-16 22:55:24 +02:00
Sebastien Bourdeauducq
31b1960188
xilinx_ise: add --no-source option to disable sourcing of ISE settings file
2013-04-16 22:39:35 +02:00
Sebastien Bourdeauducq
ceb0a99d83
Change license to 2-clause BSD
2013-04-15 23:55:30 +02:00
Sebastien Bourdeauducq
8e11fcf1d0
bus/csr/SRAM: fix Module conversion errors
2013-04-14 13:55:04 +02:00
Sebastien Bourdeauducq
ea63389823
fhdl: support len() on all values
2013-04-14 13:50:26 +02:00
Werner Almesberger
59d64e92e8
mibuild: define memory card pins of the Milkymist One platorm
...
This patch adds the memory card pins to the M1 platform definition in
mibuild.
I've tentatively named them "mmc". As far as I can tell, "MMC" is not
trademarked ("MultiMediaCard" the new "eMMC" would be), and "MMC" is
commonly used in the industry in a descriptive way to refer to this
sort of interface.
The original Verilog-based M1 calls the interface "mc", but since
several names have changed between milkymist and -ng, I thought I'd
use a more familiar name.
Usage example (clock signal divided by powers of two on the MMC TPs):
https://github.com/wpwrak/ming-ddc-debug/blob/counter-on-mmc/build.py
- Werner
2013-04-12 09:51:57 +02:00
Sebastien Bourdeauducq
75d33a0c05
fhdl/verilog/_printinit: initialize undriven Special inputs (bug reported by Florent Kermarrec)
2013-04-11 18:55:49 +02:00
Sebastien Bourdeauducq
72ef4b9683
ioo+pytholite: use new Module API
2013-04-10 23:42:46 +02:00
Sebastien Bourdeauducq
4c9018ea17
fhdl/visit: add TransformModule
2013-04-10 23:42:14 +02:00
Sebastien Bourdeauducq
746acdacd1
ioo: move to genlib
2013-04-10 22:28:53 +02:00
Sebastien Bourdeauducq
1cc4c8ee9f
uio: remove Trampoline (Python 3.3 provides generator delegation instead)
2013-04-10 22:15:28 +02:00
Sebastien Bourdeauducq
6ce856290a
flow: match record fields by position
2013-04-10 21:33:56 +02:00
Sebastien Bourdeauducq
df1ed32765
genlib/record/connect: add match_by_position
2013-04-10 21:33:45 +02:00
Sebastien Bourdeauducq
692794a21f
flow: use Module and new Record APIs
2013-04-10 19:12:42 +02:00
Sebastien Bourdeauducq
843f8a5bfc
platforms: add Papilio Pro
2013-04-08 20:28:23 +02:00
Sebastien Bourdeauducq
715d332c3d
crg: apply constraint to IO pins, not internal signals
2013-04-08 20:28:11 +02:00
Sebastien Bourdeauducq
20bdd424c8
flow: adapt to new Record API
2013-04-01 22:15:23 +02:00
Sebastien Bourdeauducq
29b468529f
bus: replace simple bus module with new bidirectional Record
2013-04-01 21:54:21 +02:00
Sebastien Bourdeauducq
6a3c413717
New bidirectional-capable Record API
2013-04-01 21:53:33 +02:00
Sebastien Bourdeauducq
c4f4143591
New CSR API
2013-03-30 17:28:41 +01:00
Sebastien Bourdeauducq
633e5e6747
fhdl/module/finalize: pass additional args to do_finalize
2013-03-30 11:29:46 +01:00
Sebastien Bourdeauducq
8cf7c96a53
crg: use new platform.request
2013-03-26 23:08:35 +01:00
Sebastien Bourdeauducq
38e92eb92b
altera_quartus: fix clock domain name
2013-03-26 23:05:46 +01:00
Sebastien Bourdeauducq
3b19dfc412
Support for platform info
2013-03-26 19:17:35 +01:00
Sebastien Bourdeauducq
74cc4d22cd
generic_platform: remove obj in request + add lookup_request
2013-03-26 17:56:53 +01:00
Sebastien Bourdeauducq
574becc1fc
fhdl/specials: clean up clock domain handling
2013-03-26 11:58:34 +01:00
Sebastien Bourdeauducq
77a0f0a3bb
actorlib/structuring/Cast: support inversion
2013-03-25 15:54:09 +01:00
Sebastien Bourdeauducq
c4c4765a4e
bank/csrgen/BankArray: retain name information
2013-03-25 14:44:15 +01:00
Sebastien Bourdeauducq
53edc3557e
bank/description/Register: add get_size
2013-03-25 14:43:44 +01:00
Sebastien Bourdeauducq
3da98ea04d
genlib/record: use getattr instead of __dict__
2013-03-24 00:51:01 +01:00
Sebastien Bourdeauducq
1897b74f97
genlib/record: add eq
2013-03-24 00:50:33 +01:00
Sebastien Bourdeauducq
003f1950cd
xilinx_ise: fix clock domain names
2013-03-23 19:37:16 +01:00
Sebastien Bourdeauducq
9d7c679b8c
genlib/fifo: simple synchronous FIFO
2013-03-22 18:18:38 +01:00
Sebastien Bourdeauducq
ca431fc7c2
fhdl/module: support clock domain remapping of submodules
2013-03-22 18:17:54 +01:00
Sebastien Bourdeauducq
a94bf3b2c5
genlib/cdc/MultiReg: output clock domain defaults to sys
2013-03-21 10:40:02 +01:00
Sebastien Bourdeauducq
b38818eb17
examples/sim/fir: convert to new API
2013-03-19 11:46:27 +01:00
Sebastien Bourdeauducq
17f2b17654
fhdl/verilog: optionally disable clock domain creation
2013-03-18 18:45:19 +01:00
Sebastien Bourdeauducq
797411c1a9
generic_platform: do not create clock domains during Verilog conversion
2013-03-18 18:44:58 +01:00
Sebastien Bourdeauducq
af4eb02551
examples/basic/arrays: demonstrate lowering of Array in Instance expression
2013-03-18 18:37:23 +01:00
Sebastien Bourdeauducq
7a06e9457c
Lowering of Special expressions + support ClockSignal/ResetSignal
2013-03-18 18:36:50 +01:00
Sebastien Bourdeauducq
dc55289323
fhdl/tools/_ArrayLowerer: complete support for arrays as targets
2013-03-18 14:38:01 +01:00
