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1,382 Commits 40 Branches 14 Tags 51 MiB
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90 Commits

Author SHA1 Message Date
Florent Kermarrec cf17f06860 targets: fix CLKIN1_PERIOD on ppro and pipistrello 2015-03-22 00:30:21 +01:00
Florent Kermarrec 30c2521eb0 sdram: pass sdram_controller_settings to SDRAMSoC 2015-03-21 23:12:18 +01:00
Florent Kermarrec 70469e1f37 sdram: simplify the way we pass settings to controller and rename ramcon_type to sdram_controller_type (more explicit) 2015-03-21 21:32:39 +01:00
Florent Kermarrec c55199deb9 misoclib/soc: add _integrated_ to cpu options to avoid confusion 2015-03-21 20:51:37 +01:00
Florent Kermarrec 711540e15c targets/mlabs_video: rename sdram_module to sdram_modules to reflect that we have 2 modules sharing the same characteristics 2015-03-21 18:10:56 +01:00
Florent Kermarrec 1c0e306176 targets/kc705: rename sdram_module to sdram_modules to reflect that we have 8 modules sharing the same characteristics 2015-03-21 18:07:10 +01:00
Florent Kermarrec 52924ee1f2 sdram: define MT46V32M16/MT8JTF12864 and use it on pipistrello/kc705 2015-03-21 17:25:36 +01:00
Florent Kermarrec fd2f8d4bb4 sdram: define MT46V32M16 and use it on m1/mixxeo 2015-03-21 17:04:58 +01:00
Florent Kermarrec de2f1c31d5 sdram: create module.py to define SDRAM modules and use it on de0nano/ppro targets 2015-03-21 16:56:53 +01:00
Florent Kermarrec 6e4b7c6cfd sdram: split sdram_timing in sdram_timing_settings/sdram_controller_settings 
req_queue_size, read_time, write_time settings are not sdram_timing settings but sdram controller settings
 2015-03-21 12:55:39 +01:00
Robert Jordens ec465959d0 pipistrello: add user reset 
apparently needed for flashed bitstream, xiped bios, mor1kx
 2015-03-19 19:01:06 +01:00
Robert Jordens a10875a3b7 pipistrello: fix flash, ddram pin naming 2015-03-19 19:01:06 +01:00
Florent Kermarrec 9f2e5cd7b6 targets/kc705: add external reset 2015-03-19 15:58:04 +01:00
Florent Kermarrec cb4be52922 targets: add Lattice ECP3 versa 2015-03-17 19:09:43 +01:00
Florent Kermarrec b2f32ad124 targets/simple: manual instantiation of CRG (automatic insertion works for BaseSoC but not for MiniSoC since this one define clock_domains) 2015-03-17 01:07:44 +01:00
Florent Kermarrec 28d04ec300 soc: rename with_sdram option to with_main_ram (with_sdram was confusing) 2015-03-14 00:49:19 +01:00
Sebastien Bourdeauducq d09529d483 targets/simple: use mibuild default clock 2015-03-14 00:11:59 +01:00
Florent Kermarrec 1b72b81f9c targets/simple: use new generic DifferentialInput 2015-03-12 18:36:04 +01:00
Florent Kermarrec f18ae9b9fe targets/simple: insert IBUFDS for Xilinx devices (not implemented for others vendors) 2015-03-12 17:25:01 +01:00
Florent Kermarrec e133777450 targets/simple: add MiniSoC 2015-03-06 10:10:58 +01:00
Florent Kermarrec 95fa753149 liteeth: add phy autodetect function (phy can still be instanciated directly) 2015-03-06 10:10:34 +01:00
Florent Kermarrec 2b9397ff5b targets: do not implement sdram if already provided by SoC (allow use of -Ot with_sdram = True) 2015-03-06 07:56:45 +01:00
Florent Kermarrec 0716dadaf2 targets: keep the SPI flash core even if with_rom is enabled, so that flash booting in the BIOS still works 2015-03-03 10:39:31 +01:00
Florent Kermarrec 02ef1dc95a targets: fix mlabs_video FramebufferSoC 2015-03-02 18:38:43 +01:00
Florent Kermarrec 473997df26 cpuif: add CSR_ prefix to CSR base addresses (avoid conflicts between CSR and mems bases) 2015-03-02 16:52:17 +01:00
Florent Kermarrec de698c51e4 sdram: rename self.phy_settings to self.settings (using phy.settings instead of phy.phy_settings seems cleaner) 2015-03-02 11:29:43 +01:00
Robert Jordens 93b80b2f1c pipistrello: fix lpddr parameters, crg, flash, style 2015-02-28 16:17:34 -07:00
Florent Kermarrec b32a0e6f9e liteeth: create example design derived from SoC that can be used on all targets with Ethernet pins 2015-02-28 23:33:00 +01:00
Florent Kermarrec 6107b7844a test implementation on all targets and fix issues 2015-02-28 12:04:51 +01:00
Florent Kermarrec 1366ff5e26 move mxcrg to others (we should integrate it in mlabs_video.py and remove the verilog file in the future) 2015-02-28 11:51:51 +01:00
Florent Kermarrec 69e869893d remane GenSoC to SoC (more coherent and we will add support for multiple SoCs with their own Wisbbone/CSR buses in the future) 2015-02-28 11:36:15 +01:00
Florent Kermarrec 2c51adcd68 misoclib: better organization (create cores categories: cpu, mem, com, ...) 2015-02-28 09:40:44 +01:00
Florent Kermarrec 074f576340 targets: add de0nano (100MHz, integrated bios and SDRAM) 2015-02-27 19:47:32 +01:00
Florent Kermarrec 5e2e9338d2 bios: we can now use -Ot with_rom True on targets to force bios implementation in integrated rom (can speed up debug we don't want to reflash SPI or NOR flash) 2015-02-27 17:22:44 +01:00
Florent Kermarrec b031c5edae targets: fix MiniSoC 2015-02-27 17:12:37 +01:00
Florent Kermarrec 07b9cabd0d gensoc: make it more generic (a SoC does not necessarily have a CPU) 2015-02-27 16:39:00 +01:00
Florent Kermarrec 367db268ad reserve csr_map 0-->16 for gensoc internal csrs 2015-02-27 14:18:13 +01:00
Florent Kermarrec 77a6f580e2 gensoc: add check_cpu_memory_region and check_csr_region to detect csr and mem regions conflicts 2015-02-27 10:23:02 +01:00
Robert Jordens 2b12679ef6 add pipistrello target 2015-02-26 21:35:42 -07:00
Sebastien Bourdeauducq a3909bb5e2 Merge branch 'master' of https://github.com/m-labs/misoc 2015-02-26 21:28:12 -07:00
Yann Sionneau 8364fe6674 target/kc705: allow access to pll_sys signal before BUFG 2015-02-26 15:56:10 -07:00
Florent Kermarrec 5e8a0c496d gensoc: add mem_map and mem_decoder to avoid duplications 2015-02-26 20:12:27 +01:00
Florent Kermarrec 554731ae44 targets/simple: make it generic (no default_platform, use platform's default_clk_name/default_clk_period) 2015-02-26 13:08:15 +01:00
Florent Kermarrec 00862a383c liteeth: fix import (from liteeth --> from misoclib.liteeth) 2015-02-26 09:48:37 +01:00
Florent Kermarrec 73ab271f9a targets/kc705: fix csr address conflict on eth 2015-02-18 10:45:18 -07:00
Florent Kermarrec 0a38b8c74a add LiteX external core and remove ethmac 2015-02-18 10:43:44 -07:00
Florent Kermarrec 9ebb8f8022 remove verilog and move mxcrg.v to misoclib/mxcrg 2015-02-18 10:40:30 -07:00
Florent Kermarrec ceb675c3f1 fix cf92821 merge issue 2014-12-19 21:49:49 +08:00
Yann Sionneau edb1622668 spiflash: BB write support 2014-11-27 23:10:39 +08:00
Yann Sionneau cf92821fcf Refactor directory hierarchy of sdram phys and controllers 2014-11-27 22:09:10 +08:00