Sebastien Bourdeauducq
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6664af73d1
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uart: new design using FHDL and bank (TX only, incomplete)
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2011-12-18 00:29:37 +01:00 |
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Sebastien Bourdeauducq
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135a2eb868
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bank: support raw registers
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2011-12-18 00:28:04 +01:00 |
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Sebastien Bourdeauducq
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d21e095397
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fhdl: fix series of if/elif/else
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2011-12-17 20:31:42 +01:00 |
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Sebastien Bourdeauducq
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1a845d4553
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32-device, 8-bit CSR bus
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2011-12-17 15:54:49 +01:00 |
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Sebastien Bourdeauducq
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bb21f7584a
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32-device, 8-bit CSR bus
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2011-12-17 15:54:42 +01:00 |
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Sebastien Bourdeauducq
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1b3edd07ca
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norflash tb: use get_fragment
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2011-12-17 15:22:26 +01:00 |
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Sebastien Bourdeauducq
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6f8a6db40a
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verilog: get the simulator to run the combinatorial process at the beginning
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2011-12-17 15:20:22 +01:00 |
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Sebastien Bourdeauducq
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0e30d67fa3
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Multiply system clock
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2011-12-17 15:00:18 +01:00 |
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Sebastien Bourdeauducq
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85fbe07b94
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clkfx module
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2011-12-17 15:00:11 +01:00 |
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Sebastien Bourdeauducq
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ec47394012
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verilog: support for float parameters in instances
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2011-12-17 14:59:27 +01:00 |
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Sebastien Bourdeauducq
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411e1af980
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Proper reset generation
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2011-12-16 22:25:26 +01:00 |
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Sebastien Bourdeauducq
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ee6ca729a2
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verilog: user-definable reset and clock
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2011-12-16 22:25:05 +01:00 |
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Sebastien Bourdeauducq
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738b45dcbd
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Support the new FHDL syntax
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2011-12-16 21:30:22 +01:00 |
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Sebastien Bourdeauducq
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c7b9dfc203
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fhdl: simpler syntax
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2011-12-16 21:30:14 +01:00 |
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Sebastien Bourdeauducq
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39b7190334
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Pay a bit more attention to PEP8
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2011-12-16 16:02:55 +01:00 |
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Sebastien Bourdeauducq
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ca68097ef6
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Pay a bit more attention to PEP8
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2011-12-16 16:02:49 +01:00 |
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Sebastien Bourdeauducq
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929cc98070
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wishbone2csr: wait for WB deack
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2011-12-13 17:38:59 +01:00 |
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Sebastien Bourdeauducq
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b487e99bcf
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Initial import
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2011-12-13 17:33:12 +01:00 |
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Sebastien Bourdeauducq
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22d03b4943
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timeline: only trigger in rest state
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2011-12-13 15:25:46 +01:00 |
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Sebastien Bourdeauducq
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6f7a35e0a3
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examples: Wishbone interconnect test bench
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2011-12-13 14:10:56 +01:00 |
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Sebastien Bourdeauducq
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c840848dba
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verilog: use blocking assignment in combinatorial process
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2011-12-13 14:09:12 +01:00 |
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Sebastien Bourdeauducq
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92f24b784d
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wishbone: decoder: fix slave cyc generation in registered mode
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2011-12-13 14:08:39 +01:00 |
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Sebastien Bourdeauducq
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0ea7a9b2e6
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wishbone2csr: fix double-write bug
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2011-12-13 00:25:46 +01:00 |
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Sebastien Bourdeauducq
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923fc52e68
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wishbone: only send ack to the active master in arbiter
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2011-12-13 00:25:25 +01:00 |
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Sebastien Bourdeauducq
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a72faaecdd
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fhdl: allow a namespace to be specified for Verilog conversion
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2011-12-13 00:24:40 +01:00 |
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Sebastien Bourdeauducq
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eee6980a36
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fhdl: support Constant parameters for Verilog conversion
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2011-12-11 20:17:51 +01:00 |
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Sebastien Bourdeauducq
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dafef5d744
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fhdl: fix list references (thanks Lars)
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2011-12-11 20:17:29 +01:00 |
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Sebastien Bourdeauducq
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16a6029a1b
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bus: fix CSR interconnect data readback
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2011-12-11 20:17:12 +01:00 |
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Sebastien Bourdeauducq
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dad9120653
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bus: 14-bit CSR addresses
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2011-12-11 20:16:50 +01:00 |
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Sebastien Bourdeauducq
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7582b76406
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bank: fix csrgen address decoder
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2011-12-11 20:15:30 +01:00 |
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Sebastien Bourdeauducq
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05d91c7104
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bus: Wishbone to CSR bridge
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2011-12-11 15:04:34 +01:00 |
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Sebastien Bourdeauducq
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af74a89b8a
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corelogic: timeline module
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2011-12-11 01:11:13 +01:00 |
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Sebastien Bourdeauducq
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019ef16db4
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fhdl: remove broken fragment iadd
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2011-12-11 01:10:59 +01:00 |
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Sebastien Bourdeauducq
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b00581616e
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convtools: insert reset on variables
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2011-12-11 01:10:37 +01:00 |
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Sebastien Bourdeauducq
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d3127fd5d8
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autofragment: remove debug
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2011-12-10 20:48:23 +01:00 |
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Sebastien Bourdeauducq
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44f44b8a05
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fhdl: autofragment
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2011-12-10 20:47:21 +01:00 |
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Sebastien Bourdeauducq
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4b15a84505
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fhdl: fix += for empty fragment
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2011-12-10 20:47:06 +01:00 |
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Sebastien Bourdeauducq
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a49ecc4331
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fhdl: pad support in fragments
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2011-12-10 20:25:24 +01:00 |
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Sebastien Bourdeauducq
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4d1a960308
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wishbone: decoder + shared bus interconnect
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2011-12-09 13:11:52 +01:00 |
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Sebastien Bourdeauducq
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fa63cc1ec8
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fhdl: replication support
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2011-12-09 13:11:34 +01:00 |
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Sebastien Bourdeauducq
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5c7131dc86
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wishbone: arbiter
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2011-12-08 23:21:25 +01:00 |
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Sebastien Bourdeauducq
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c1041b9a5f
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simplebus: export GetSigName function
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2011-12-08 23:06:04 +01:00 |
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Sebastien Bourdeauducq
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b2bc5ad4f4
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corelogic: multimux module
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2011-12-08 23:04:34 +01:00 |
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Sebastien Bourdeauducq
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b0c5b74c22
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verilog: handle default in case statements
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2011-12-08 23:04:20 +01:00 |
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Sebastien Bourdeauducq
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512655c108
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fhdl: improve automatic signal naming
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2011-12-08 21:28:20 +01:00 |
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Sebastien Bourdeauducq
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5034af3038
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Corelogic conversion example
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2011-12-08 21:25:05 +01:00 |
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Sebastien Bourdeauducq
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62f70a54f0
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corelogic: MC divider module
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2011-12-08 21:19:40 +01:00 |
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Sebastien Bourdeauducq
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84eb964adc
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fhdl: support negation operator
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2011-12-08 21:15:44 +01:00 |
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Sebastien Bourdeauducq
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bf021efa2b
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verilog: fix unary operator conversion
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2011-12-08 21:15:24 +01:00 |
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Sebastien Bourdeauducq
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78f18ad593
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corelogic: round-robin module
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2011-12-08 21:15:02 +01:00 |