Commit Graph

4741 Commits

Author SHA1 Message Date
Florent Kermarrec e8e57b4f87 soc_core: cleanup/re-align 2019-09-29 17:31:37 +02:00
Florent Kermarrec 334ae336bf soc/integration: rename cpu_interface to export (with retro-compat), re-arrange a bit, add separators 2019-09-29 17:23:26 +02:00
Florent Kermarrec 241c3c642b test/test_targets: update cpu-type to mor1kx 2019-09-29 17:12:15 +02:00
Florent Kermarrec 48e5a1d140 soc/cores: uniformize (continue) 2019-09-29 17:04:21 +02:00
Florent Kermarrec e9ed4761b5 soc/cores/gpio: uniformize with others cores 2019-09-29 16:10:44 +02:00
Florent Kermarrec 78cecbe36b soc/cores: rename frequency_meter to freqmeter and uniformize with others cores 2019-09-29 16:08:39 +02:00
Florent Kermarrec 7575ecc6ad soc/cores/ecc: improve readibility, uniformize with others cores 2019-09-29 16:02:04 +02:00
Florent Kermarrec c6fe3f3145 soc/cores/clocks: improve readibility 2019-09-29 15:58:22 +02:00
Florent Kermarrec 6fcb12a98f soc_core: use cpu.data_width to compute csr_alignment (and remove Rocket workaround) 2019-09-29 15:47:10 +02:00
Florent Kermarrec b826c1705f soc/cores/cpus: improve ident/align, uniformize between cpus 2019-09-29 15:41:36 +02:00
Florent Kermarrec 355072c285 soc/cores/cpu: add CPU class and make all CPU inheritate from it
Also rename reserved_interrupts to interrupts (empty dict is no reserved interrupts)
2019-09-29 15:27:41 +02:00
Florent Kermarrec 2c3ad3f96d soc_sdram: move ControllerInjector to LiteDRAM (LiteDRAMCore) 2019-09-29 14:44:44 +02:00
Florent Kermarrec 101f1b1cef soc/integration: add common.py and move helpers from soc_core to it 2019-09-29 14:22:26 +02:00
Florent Kermarrec 68ba1c60be soc_core: avoid manual listing of support CPUs, just use CPU.keys() 2019-09-28 22:19:23 +02:00
Florent Kermarrec 9095b80e89 soc_core: remove add_cpu_or_bridge retro-compatibility (most of the designs have been updated since the change) 2019-09-28 19:01:41 +02:00
Florent Kermarrec 8dd2dc1ce8 integration/soc_core: remove csr_map_update (no longer used) 2019-09-28 18:59:30 +02:00
Florent Kermarrec da91aa43f7 soc_core/cpu: move memory map override to CPUs, select reset_address after eventual memory map has override been done 2019-09-28 14:15:48 +02:00
Florent Kermarrec 8099b0beb6 soc/cores/cpu: add set_reset_address method and use it instead of passing reset_address as a parameter 2019-09-28 12:35:41 +02:00
Florent Kermarrec 7660dc22e1 soc/cores/cpu: do instance in do_finalize for all cpus (allow updating parameters until the design is generated) 2019-09-28 12:09:55 +02:00
Florent Kermarrec a3816096a7 cores/cpu: define CPUS and simplify instance 2019-09-28 00:55:08 +02:00
Florent Kermarrec 9f6a2ae73e soc_core/serv: use UART_POLLING (no interrupt support) 2019-09-28 00:42:00 +02:00
Florent Kermarrec a4069fc863 add SERV submodule 2019-09-28 00:41:28 +02:00
Florent Kermarrec 49594ed7d4 software/libbase/uart: add polling mode 2019-09-28 00:35:26 +02:00
Florent Kermarrec 3f95b9c0de add SERV CPU initial support (not working) 2019-09-28 00:34:55 +02:00
Florent Kermarrec 015b65fe88 targets/ulx3s: revert to cl=2 2019-09-25 14:09:44 +02:00
Florent Kermarrec a9d55b04c0 boards/netv2: switch to MVP, add spiflashx4 and hdmi in/out 2019-09-25 14:07:28 +02:00
Florent Kermarrec 1425a68d9e wishbone2csr: refactor using FSM, reduce latency (make it asynchronous) and set csr.adr only when access is done (allow use of CSR/CSRBase we signal)
Making it asynchronous does not seem to deteriorate timing or resource usage, if it's the case for some designs, we'll add a register parameter.
2019-09-24 17:55:29 +02:00
Florent Kermarrec ffd2be2ba0 csr: add we signal to CSR, CSRStatus
Doing actions on register read is generally not a good design practice (it's
better to do separate register write to trigger actions) but in some very
specific cases being able to know that register has been read can solve cases
that are difficult to do with the recommended practives and that can justify
doing an exception.


This commit add a we signal to CSR, CSRStatus and this allow the logic to know
when the CSR, CSRStatus is read.
2019-09-24 17:51:06 +02:00
Florent Kermarrec 47dc332498 build/xilinx/programmer: fix vivado_cmd 2019-09-24 14:40:48 +02:00
Florent Kermarrec ed9bff2eb9 soc/integration/doc: replace "== None" by "is None" 2019-09-24 10:11:31 +02:00
enjoy-digital 836d5b88c5
Merge pull request #266 from xobs/add-moduledoc-autodoc
Add ModuleDoc and AutoDoc
2019-09-24 10:09:22 +02:00
Florent Kermarrec 78fb0fb9dc tools/litex_read_verilog: also delete yosys_v2j.ys 2019-09-24 08:49:00 +02:00
Benjamin Herrenschmidt 0ea7a1fd05 soc_core/sdram: Don't blow up if _wb_sdram_ifs or _csr_masters are empty
For example a standalone controller with no exposed CSRs (probably not
a very useful configuration but I really don't like python backtraces)

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2019-09-24 08:41:59 +02:00
Sean Cross 68cea8c32f timer: inherit ModuleDoc
With the new ModuleDoc class, we can inherit `ModuleDoc` and
automatically get module-level documentation.

This patch also corrects a typo in `timer` that causes an error in
sphinx.

Signed-off-by: Sean Cross <sean@xobs.io>
2019-09-24 14:34:41 +08:00
Sean Cross 131971986c integration: add ModuleDoc and AutoDoc
It is important to be able to document modules other than CSRs.
This patch adds ModuleDoc and AutoDoc, both of which can be used
together to document modules.

ModuleDoc can be used to transform the __doc__ string of a class into a
reference-manual section.  Alternately, it can be used to add additional
sections to a module.

AutoDoc is used to gather all submodule ModuleDoc objects in order to
traverse the tree of documentation.

Signed-off-by: Sean Cross <sean@xobs.io>
2019-09-24 14:30:28 +08:00
enjoy-digital 742da31bc0
Merge pull request #264 from antmicro/mor1kx_linux
Enable to run Linux on mork1x
2019-09-23 23:19:45 +02:00
Florent Kermarrec 06d0806494 soc_core: set csr to 0x00000000 when there is no wishbone 2019-09-23 15:57:14 +02:00
Florent Kermarrec ad8830d977 soc_sdram: Don't add the L2 Cache when there's no wishbone bus 2019-09-23 15:53:07 +02:00
Filip Kokosinski 5844376d53 soc_core: adapt memory map for mainline Linux with mor1kx
Mainline Linux expects it to be loaded at the physical address of 0x0.
Change the MAIN_RAM base address to 0x0 and update exception vector
during the booting process.
2019-09-23 15:34:52 +02:00
Filip Kokosinski 201218b2c3 boards/targets: increase integrated ROM size if EthernetSoC is used
Currently section '.rodata' of the LiteX BIOS doesn't fit in the 'rom'
region if mor1kx is used with EthernetSoC. Increase the integrated ROM
size from 0x8000 to 0x10000 in EthernetSoC.
2019-09-23 15:34:34 +02:00
Florent Kermarrec ae38fd4244 soc_core: revert wishbone2csr to __init__ but add with_wishbone parameter 2019-09-23 12:59:43 +02:00
Florent Kermarrec 8c979565a8 soc_sdram: change l2_size checks order 2019-09-23 10:15:27 +02:00
Florent Kermarrec a9acab99b3 soc_core: move CSR bridge to finalize (only generate it if there is a wishbone master), revert default parameter when cpu_type is None (we have systems with cpu_type=None but that are using these peripherals) 2019-09-23 09:58:47 +02:00
Florent Kermarrec dde6dd027b integration/builder: avoid specific _generate_standalone_includes 2019-09-23 09:26:47 +02:00
Benjamin Herrenschmidt 735ea196dd This will allow it to be built for microwatt out of tree
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2019-09-23 08:40:54 +02:00
Benjamin Herrenschmidt c28086cde8 soc_core: When cpu_type is "None", let's not generate useless UART, timer, ROMs, wishbone to CSR bridge etc...
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2019-09-23 08:35:50 +02:00
Benjamin Herrenschmidt f909e4d706 integration/builder: When the CPU is "None", we used to not generate any code.
With this change, we will now generate csr.h and sdram_phy.h, which
will be needed by the initialization code running on the host CPU.

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2019-09-23 08:31:21 +02:00
enjoy-digital 8b7d8217a0
Merge pull request #263 from xobs/spi-flash-csrfield
spi_flash: document register fields
2019-09-20 08:28:19 +02:00
Sean Cross 1a6dddd57c spi_flash: document register fields
Document the various fields present in the SPI flash bitbang interface.
This adds documentation for the Single and DualQuad modules.

Signed-off-by: Sean Cross <sean@xobs.io>
2019-09-20 12:42:43 +08:00
enjoy-digital 4f659ba422
Merge pull request #262 from jersey99/master
vivado just needs to be in the path for the programmer as well
2019-09-20 06:25:57 +02:00