177 commits

Author	SHA1	Message	Date
Sebastien Bourdeauducq	f202946717	fhdl/tools/_TargetLister: do not include array keys in targets	2013-05-11 17:28:41 +02:00
Sebastien Bourdeauducq	b862b070d6	fhdl/verilog: recursive Special lowering	2013-04-25 14:56:26 +02:00
Sebastien Bourdeauducq	fee228a09f	fhdl/specials/memory: do not write address register for async reads	2013-04-25 13:30:05 +02:00
Florent Kermarrec	f599fe4ade	Support for resetless clock domains	2013-04-23 11:54:05 +02:00
Sebastien Bourdeauducq	ea63389823	fhdl: support len() on all values	2013-04-14 13:50:26 +02:00
Sebastien Bourdeauducq	75d33a0c05	fhdl/verilog/_printinit: initialize undriven Special inputs (bug reported by Florent Kermarrec)	2013-04-11 18:55:49 +02:00
Sebastien Bourdeauducq	4c9018ea17	fhdl/visit: add TransformModule	2013-04-10 23:42:14 +02:00
Sebastien Bourdeauducq	633e5e6747	fhdl/module/finalize: pass additional args to do_finalize	2013-03-30 11:29:46 +01:00
Sebastien Bourdeauducq	574becc1fc	fhdl/specials: clean up clock domain handling	2013-03-26 11:58:34 +01:00
Sebastien Bourdeauducq	ca431fc7c2	fhdl/module: support clock domain remapping of submodules	2013-03-22 18:17:54 +01:00
Sebastien Bourdeauducq	17f2b17654	fhdl/verilog: optionally disable clock domain creation	2013-03-18 18:45:19 +01:00
Sebastien Bourdeauducq	7a06e9457c	Lowering of Special expressions + support ClockSignal/ResetSignal	2013-03-18 18:36:50 +01:00
Sebastien Bourdeauducq	dc55289323	fhdl/tools/_ArrayLowerer: complete support for arrays as targets	2013-03-18 14:38:01 +01:00
Sebastien Bourdeauducq	e95d2f4779	fhdl/tools/value_bits_sign: support not	2013-03-18 09:52:43 +01:00
Sebastien Bourdeauducq	b6fe3ace05	fhdl/structure: style fix	2013-03-17 15:33:38 +01:00
Sébastien Bourdeauducq	2a4cc3875c	Merge pull request #6 from larsclausen/master ... Minor improvements	2013-03-17 07:33:14 -07:00
Sebastien Bourdeauducq	7b49fd9386	fhdl/specials: fix rename_clock_domain declarations	2013-03-15 19:47:01 +01:00
Sebastien Bourdeauducq	dd0f3311cd	structure: remove Fragment.call_sim	2013-03-15 19:15:48 +01:00
Sebastien Bourdeauducq	bd8bbd9305	Make ClockDomains part of fragments	2013-03-15 18:17:33 +01:00
Lars-Peter Clausen	72579a6129	Add support for negative slice indices ... In python a negative indices usually mean start counting from the right side. I.e. if the index is negative is acutal index used is len(l) + i. E.g. l[-2] equals l[len(l)-2]. Being able to specify an index this way also comes in handy for migen slices in some cases. E.g. the following snippet can be implement to shift an abitrary length register n bits to the right: reg.eq(Cat(Replicate(0, n), reg[-n:]) Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>	2013-03-12 21:56:01 +01:00
Sebastien Bourdeauducq	ecfe1646ec	fhdl/verilog: implicit get_fragment	2013-03-12 16:16:06 +01:00
Sebastien Bourdeauducq	4ada2ead05	fhdl/specials/Memory: automatic name#	2013-03-12 15:58:39 +01:00
Sebastien Bourdeauducq	04df076fba	bank: automatic register naming	2013-03-12 15:45:24 +01:00
Sebastien Bourdeauducq	7e2581bf17	fhdl/tracer: recognize CALL_FUNCTION_VAR opcode	2013-03-12 13:48:09 +01:00
Sebastien Bourdeauducq	12158ceadf	fhdl/tracer: recognize LOAD_DEREF opcode	2013-03-12 10:31:56 +01:00
Sebastien Bourdeauducq	3c75121783	fhdl/tracer: remove leading underscores from names	2013-03-11 22:21:58 +01:00
Sebastien Bourdeauducq	17e0dfe120	fhdl/module: replace autofragment	2013-03-10 19:27:55 +01:00
Sebastien Bourdeauducq	d0676e2dd1	migen/fhdl/autofragment: factorize	2013-03-09 23:23:24 +01:00
Sebastien Bourdeauducq	d0d2df3c4b	fhdl/autofragment: remove legacy functions	2013-03-09 23:05:45 +01:00
Sebastien Bourdeauducq	72fb6fd6bd	fhdl/tools/flat_iteration: generalize	2013-03-09 23:03:15 +01:00
Sebastien Bourdeauducq	f53acb92e7	fhdl/autofragment: fix submodules	2013-03-09 21:15:38 +01:00
Sebastien Bourdeauducq	6da8eb906f	fhdl/autofragment: empty build_fragment by default	2013-03-09 19:10:47 +01:00
Sebastien Bourdeauducq	2b8dc52c13	Use common definition for FinalizeError	2013-03-09 19:03:13 +01:00
Sebastien Bourdeauducq	6fa30053bf	fhdl/verilog: tristate outputs are always wire	2013-03-06 11:30:52 +01:00
Sebastien Bourdeauducq	bb5ee8d3bd	fhdl/autofragment: bugfixes + add auto_attr	2013-03-03 17:53:06 +01:00
Sebastien Bourdeauducq	cc8118d35c	fhdl/autofragment: FModule	2013-03-02 23:30:54 +01:00
Sebastien Bourdeauducq	c10622f5e2	fhdl/verilog: insert reset before listing signals	2013-02-27 18:10:04 +01:00
Sebastien Bourdeauducq	a81781f589	fhdl/specials: allow setting memory name	2013-02-25 23:14:03 +01:00
Sebastien Bourdeauducq	55ab01f928	fhdl/specials/Instance: _printintbool -> verilog_printexpr	2013-02-24 13:08:01 +01:00
Sebastien Bourdeauducq	7c4e6c35e5	fhdl/verilog: support special lowering and overrides	2013-02-23 19:03:16 +01:00
Sebastien Bourdeauducq	38664d6e16	fhdl: inline synthesis directive support	2013-02-22 19:10:02 +01:00
Sebastien Bourdeauducq	49cfba50fa	New 'specials' API	2013-02-22 17:56:35 +01:00
Sebastien Bourdeauducq	1b18194b1d	fhdl: TSTriple	2013-02-19 17:26:02 +01:00
Sebastien Bourdeauducq	dc93a231c6	fhdl: tristate support	2013-02-15 00:17:24 +01:00
Sebastien Bourdeauducq	63d399b6ad	fhdl/autofragment: from_attributes	2013-02-11 18:34:01 +01:00
Sebastien Bourdeauducq	473fd20f8c	fhdl/structure: store clock domain name	2013-01-24 13:49:49 +01:00
Sebastien Bourdeauducq	3201554f76	fhdl/verilog: fix spurious clock/reset signals on multiple calls to convert()	2013-01-23 15:13:06 +01:00
Sebastien Bourdeauducq	badba89686	fhdl: support nested statement lists	2013-01-05 14:18:15 +01:00
Sebastien Bourdeauducq	3fae6c8f03	Do not use super()	2012-12-18 14:54:33 +01:00
Sebastien Bourdeauducq	b06fbdedd6	fhdl/tools: bitreverse	2012-12-14 23:56:16 +01:00