Sebastien Bourdeauducq
|
f2c20e4af0
|
bus/asmibus/hub: hack to prevent comb loops
|
2012-04-30 17:11:42 -05:00 |
|
Sebastien Bourdeauducq
|
398ece8fe2
|
fhdl/verilog: add option to display which comb blocks are run
This is a debug hack to help find combinatorial loops in designs.
|
2012-04-30 16:38:40 -05:00 |
|
Sebastien Bourdeauducq
|
0b62e573ae
|
sim: pass extra keyword arguments to Verilog converter
|
2012-04-30 16:38:17 -05:00 |
|
Sebastien Bourdeauducq
|
6a52e44d09
|
fhdl: support len() on signals
|
2012-04-08 18:06:22 +02:00 |
|
Sebastien Bourdeauducq
|
b9c533be51
|
bank/csrgen: allow specifying existing CSR interface
|
2012-04-06 14:59:09 +02:00 |
|
Sebastien Bourdeauducq
|
2a4e49e381
|
fhdl: phase out pads
|
2012-04-02 19:21:43 +02:00 |
|
Sebastien Bourdeauducq
|
623e8e436a
|
fhdl/verilog: do not attempt to initialize instance and mem output signals
|
2012-04-02 12:59:42 +02:00 |
|
Sebastien Bourdeauducq
|
6e3b25ebb6
|
bus/dfi: reset active low signals to 1
|
2012-04-01 17:43:24 +02:00 |
|
Sebastien Bourdeauducq
|
d3c6b8d16f
|
sim/proxy: support lists
|
2012-04-01 17:19:53 +02:00 |
|
Sebastien Bourdeauducq
|
f3ae22f488
|
fhdl/verilog: initialize internal read-only signals with their reset values
|
2012-04-01 16:39:11 +02:00 |
|
Sebastien Bourdeauducq
|
0dfc215fe8
|
corelogic/roundrobin: handle correctly special case with 1 request source
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2012-03-31 18:01:40 +02:00 |
|
Sebastien Bourdeauducq
|
94b02aa8ed
|
bus/asmicon: initiator
|
2012-03-30 22:16:31 +02:00 |
|
Sebastien Bourdeauducq
|
bb864c65dc
|
sim: proxy
|
2012-03-30 16:40:26 +02:00 |
|
Sebastien Bourdeauducq
|
081b658e2d
|
Update copyright notices
|
2012-03-23 16:41:30 +01:00 |
|
Sebastien Bourdeauducq
|
d47b564fad
|
corelogic/fsm: typo
|
2012-03-18 22:12:46 +01:00 |
|
Sebastien Bourdeauducq
|
5f28103769
|
corelogic/fsm: delayed enters
|
2012-03-18 00:09:40 +01:00 |
|
Sebastien Bourdeauducq
|
a4294762d0
|
corelogic/roundrobin: CE switching
|
2012-03-16 16:54:47 +01:00 |
|
Sebastien Bourdeauducq
|
e969b9afc3
|
corelogic: convert timeline to function and move to misc
|
2012-03-15 20:25:44 +01:00 |
|
Sebastien Bourdeauducq
|
1665f293a6
|
bus/asmibus/hub: require finalization before get_slots
|
2012-03-14 16:19:29 +01:00 |
|
Sebastien Bourdeauducq
|
5c0cc6292c
|
fhdl: export log2_int
|
2012-03-14 12:19:42 +01:00 |
|
Sebastien Bourdeauducq
|
bfcd4e636b
|
fhdl: handle negative constants correctly
|
2012-03-08 20:49:24 +01:00 |
|
Sebastien Bourdeauducq
|
ab800fa2ed
|
bus: generic transaction model
|
2012-03-08 18:14:06 +01:00 |
|
Sebastien Bourdeauducq
|
678a89d572
|
sim: fix zero encoding
|
2012-03-08 15:34:08 +01:00 |
|
Sebastien Bourdeauducq
|
decbd069fa
|
sim: fix message debug formatting
|
2012-03-08 15:27:35 +01:00 |
|
Sebastien Bourdeauducq
|
98e96b3952
|
sim: make initialization cycle optional (selectable by function attribute)
|
2012-03-06 19:43:59 +01:00 |
|
Sebastien Bourdeauducq
|
8160ced2e9
|
sim: memory access
|
2012-03-06 19:29:39 +01:00 |
|
Sebastien Bourdeauducq
|
db8f8bf2e3
|
fhdl: register memory objects with namespace
|
2012-03-06 18:33:44 +01:00 |
|
Sebastien Bourdeauducq
|
6f829c7afc
|
sim: support for signed numbers
|
2012-03-06 16:46:18 +01:00 |
|
Sebastien Bourdeauducq
|
90184b22d2
|
fhdl/verilog: fix signed constant conversion
|
2012-03-06 16:45:44 +01:00 |
|
Sebastien Bourdeauducq
|
9da512dbf5
|
sim: VCD generation
|
2012-03-06 15:26:04 +01:00 |
|
Sebastien Bourdeauducq
|
22b3c11b93
|
sim: clean startup/shutdown
|
2012-03-06 15:00:02 +01:00 |
|
Sebastien Bourdeauducq
|
06de17b16c
|
sim: remove temporary files and socket
|
2012-03-06 14:20:26 +01:00 |
|
Sebastien Bourdeauducq
|
7230508e7c
|
fhdl/namer: do not reference objects with __del__ methods to avoid uncollectable cycles
|
2012-03-06 14:18:22 +01:00 |
|
Sebastien Bourdeauducq
|
2c375e900f
|
sim: remove default sockaddr
|
2012-03-06 13:58:49 +01:00 |
|
Sebastien Bourdeauducq
|
8d16fde48c
|
fhdl: add simulation functions in fragment
|
2012-03-06 13:58:22 +01:00 |
|
Sebastien Bourdeauducq
|
aac9752558
|
sim: basic functionality working
|
2012-03-05 20:31:41 +01:00 |
|
Sebastien Bourdeauducq
|
29859acc34
|
sim: two way IPC working
|
2012-03-04 19:17:03 +01:00 |
|
Sebastien Bourdeauducq
|
8586daf2dd
|
sim: IPC module (lacks str/int encoding)
|
2012-03-03 18:55:38 +01:00 |
|
Sebastien Bourdeauducq
|
1b8cb5b46c
|
bus/dfi: fix multiphase naming
|
2012-02-19 17:57:04 +01:00 |
|
Sebastien Bourdeauducq
|
d8d4e81b6e
|
bank/csrgen: fix RE generation
|
2012-02-18 18:56:18 +01:00 |
|
Sebastien Bourdeauducq
|
55a265d967
|
bank: add RE signal for registers made of fields
|
2012-02-17 23:52:06 +01:00 |
|
Sebastien Bourdeauducq
|
92dfbb92dd
|
bus: add interconnect statements function
|
2012-02-17 23:51:32 +01:00 |
|
Sebastien Bourdeauducq
|
f995e8b92e
|
fhdl: check we pass BV to signals
|
2012-02-17 23:50:54 +01:00 |
|
Sebastien Bourdeauducq
|
a1ad30faab
|
fhdl/verilog: properly connect instance inouts
|
2012-02-17 11:08:41 +01:00 |
|
Sebastien Bourdeauducq
|
ca7056b07f
|
fhdl: support forwarding of bidirectional signals from instance ports
|
2012-02-16 18:34:32 +01:00 |
|
Sebastien Bourdeauducq
|
c08687b9c6
|
bus/dfi: filter signals by direction
|
2012-02-15 21:48:05 +01:00 |
|
Sebastien Bourdeauducq
|
ef7aea0f31
|
bank: omit device write register when access_bus==READ_ONLY and access_dev==WRITE_ONLY
|
2012-02-15 18:23:31 +01:00 |
|
Sebastien Bourdeauducq
|
fa9cf3e466
|
bus: add DFI
|
2012-02-15 18:09:14 +01:00 |
|
Sebastien Bourdeauducq
|
91e279ee04
|
bank/csrgen: use new bus API
|
2012-02-15 16:42:17 +01:00 |
|
Sebastien Bourdeauducq
|
af5230c8ee
|
bus: fix simple interconnect
|
2012-02-15 16:42:05 +01:00 |