f8c5821658
Revert "gen/fhdl/verilog: allow single element verilog inline attribute"
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This reverts commit b845755995
2019-12-19 08:53:44 +01:00
f883f0c703
cpu/microwatt: add submodule
2019-12-18 19:07:08 +01:00
5da0bcbd7a
cpu/microwatt: set csr to 0xc0000000 (IO region)
2019-12-18 08:59:35 +01:00
39a8ebe70c
cpu/microwatt: fix add_source/add_sources
2019-12-18 08:56:36 +01:00
d74a7463e0
soc/cores/pwm: remove debug print(n)
2019-12-18 08:47:56 +01:00
bd15f07cf7
platforms/netv2: add xc7a100t support
2019-12-17 09:47:31 +01:00
76e57414c3
platforms/minispartan6: add assert on available devices
2019-12-17 09:47:12 +01:00
bfe0bf6402
cpu/microwatt: simplify add_sources
2019-12-17 09:41:46 +01:00
b9edde20de
cpu/microwatt: add io_regions and gcc_flags
2019-12-17 09:33:46 +01:00
16e7c6b634
cpu/microwatt: update copyright
2019-12-17 09:27:19 +01:00
3d79324fce
cpu/microwatt: drive stall signal (no burst support)
2019-12-16 12:37:27 +01:00
da3a178bc6
soc/cores/pwm: add clock_domain support
2019-12-16 11:13:10 +01:00
9da28c4ea5
build/xilinx/XilinxMultiRegImpl: fix n=0 case
2019-12-16 11:12:38 +01:00
ec7dc2d8f4
build/xilinx/ise: cleanup/simplify pass, remove mist support (not aware of anyone using it)
2019-12-14 22:47:07 +01:00
1b963bb2d5
soc/cores/cpu: add initial Microwatt gateware support
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Implementation tested on arty:
cd litex/soc/cores/cpu/microwatt
git clone https://github.com/antonblanchard/microwatt
mv microwatt sources
cd litex/boards/targets
./arty --cpu-type=microwatt --no-compile-gateware
2019-12-14 00:00:13 +01:00
c34255d2ab
soc/cores/cpu/minerva: add self.reset to i_rst
2019-12-14 00:00:07 +01:00
8b6f9e0a2c
Merge pull request #315 from gsomlo/gls-csr-assert
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soc_core: additional CSR safety assertions
2019-12-13 21:57:14 +01:00
a0dad1b071
soc_core: additional CSR safety assertions
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Since csr_data_width=64 has probably never worked properly, remove
it as one of the possible options (to be fixed and re-added later).
Add csr_data_width=16, which has been tested and does work.
Additionally, ensure csr_data_width <= csr_alignment (we should not
attempt to create (sub)registers larger than the CPU's native word
size or XLen).
Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
2019-12-12 13:14:16 -05:00
fb6b0786b6
soc_core: remove static 16MB csr region allocation (use csr_address_width to allocate the correct size)
2019-12-12 12:41:47 +01:00
b1a1e5e227
soc_core: add sort of CSR regions by origin (allow csr.h/csr.csv to be ordered by origin)
2019-12-12 11:27:56 +01:00
061d593de3
cores/8b10b: use real Memory for 6b5b table (to improve timings on ECP5)
2019-12-09 19:25:38 +01:00
a0122f9863
build/xilinx/vivado: move build_script generation
2019-12-08 12:19:38 +01:00
18ff8f38d1
build/xilinx/vivado: cleanup/simplify
2019-12-08 12:08:17 +01:00
0931ccc919
build/lattice/icestorm: cleanup/simplify (and remove arachne-pnr support)
2019-12-07 22:11:17 +01:00
b1b920531a
build/xilinx/common/platform/programmer: cleanup pass
2019-12-06 22:23:04 +01:00
edaa66bbed
boards: add Lambdaconcept's PCIe Screamer (R02)
2019-12-06 18:20:59 +01:00
a8635c48a4
targets/versa_ecp5: fix compilation with diamond
2019-12-06 16:15:08 +01:00
30a18808ad
boards/targets: keep attributes are no longer needed since automatically added when applying constraints to signals.
2019-12-06 15:58:06 +01:00
23c33cfa99
build: automatically add keep attribute to signals with timing constraints.
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Avoid having to specify it manually or eventually forget to do it and have a constraints that is not applied correctly.
2019-12-06 15:41:15 +01:00
4c9af635d2
build/altera/quartus: allow adding period constraints on nets and add optional additional sdc/qsf commands
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Additional sdc/qsf commands can be added from the design like:
platform.sdc_additional_commands.append("create_clock ...")
platform.sdc_additional_commands.append("set_false_path ...")
2019-12-06 15:19:07 +01:00
22e6f5ac1d
build/lattice/trellis: nextpnr now handle LPF timing constraints and multiple clock domains, freq_constraint is no longer needed.
2019-12-06 12:57:59 +01:00
8fb3f9a90d
build/lattice: cleanup/simplify (no functional changes)
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icestorm still need to be cleaned up
2019-12-06 12:54:52 +01:00
946478a71e
build/lattice: cleanup/simplify
2019-12-06 12:13:20 +01:00
60edca2345
build/microsemi: cleanup/simplify (no functional change)
2019-12-06 12:12:43 +01:00
50fdc5ce41
build/altera: cleanup/simplify (no functional change)
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Altera build backend was a bit messy and needed some cleanup to ease future maintenance and new features.
2019-12-06 11:08:46 +01:00
b17dfafa55
Merge pull request #313 from mmicko/yosys_ise_flow_fix
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Yosys - ISE flow fix
2019-12-05 19:05:44 -08:00
8d90f4e97b
build/xilinx/vivado: use VHDL 2008 as default
2019-12-03 15:27:20 +01:00
cfd17321e2
targets/nexys4ddr: remove MEMTEST_ADDR_SIZE limitation (no longer needed)
2019-12-03 10:11:15 +01:00
201d60f37a
targets/netv2: switch to MVP DDR3 (K4B2G1646F instead of MT41J128M16)
2019-12-03 09:05:52 +01:00
6b82064723
targets: uniformize, improve presentation
2019-12-03 08:58:01 +01:00
718f69953b
README: fix LitePCIe Travis-CI link
2019-12-02 11:03:42 +01:00
6de20f185a
soc/interconnect/csr: add fields support for CSRStorage's write simulation method
2019-12-02 09:44:44 +01:00
2567a0ae1d
soc/cores/gpio: add GPIO Tristate
2019-12-01 21:26:37 +01:00
d702c0fe35
setup.py: update long_description
2019-11-30 19:30:50 +01:00
c9665aed38
README.md: use litex logo
2019-11-30 19:23:34 +01:00
82819dd536
README: switch to Markdown
2019-11-30 19:18:47 +01:00
90f9ffc505
Merge pull request #311 from kbeckmann/trellis_cabga256
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trellis: Support the CABGA256 package
2019-11-29 19:05:56 -08:00
f411d6d362
trellis: Support the CABGA256 package
2019-11-30 02:50:41 +01:00
783dfa508c
Properly select family for those currently supported
2019-11-29 19:11:22 +01:00
6560911df2
Integrate with latest yosys changes
2019-11-29 17:12:08 +01:00
Arnaud Durand
Florent Kermarrec
Gabriel Somlo
Tim Ansell
Konrad Beckmann
Miodrag Milanovic