b8e22fcd79
interconnect/axi: Simplify/Fix IOs generation. (Param signals were missing for AXIFull).
2022-09-22 09:54:58 +02:00
162a0a4c1e
cpu/rocket: fix variant typos
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The `fulld` and `fullq` variants point to the wrong (`LitexFullConfig`)
verilog. Fix by pointing to the correct code (`LitexFullDConfig` and
`LitexFullQConfig`, respectively).
Reported-by: Ioannis Ioannou <roryt@roryt.gr>
Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
2022-09-20 09:29:46 -04:00
cb8e0193fc
Added retransmission logic for EtherBone UDP reads.
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Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
2022-09-20 09:26:24 +02:00
e12af4f050
interconnect/axi/axi_stream: Fix get_ios and base it on length of created Endpoint's signals.
2022-09-20 09:08:22 +02:00
23db2e65f4
Merge pull request #1437 from trabucayre/yosys_nextpnr_refactor_args
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build/yosys,nextpnr, lattice: refactor args
2022-09-19 19:29:34 +02:00
e9f6642d8f
build/yosys,nextpnr, lattice: refactor args
2022-09-19 19:08:25 +02:00
32272ba855
axi/axi_stream: Set default keep_width to None and automatically set it to data_width//8 when not specified.
2022-09-19 13:28:42 +02:00
860c757f33
Merge pull request #1435 from gsomlo/gls-yosys-flow3
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yosys_nextpnr_toolchain: add flow3 option to abc9 mode
2022-09-19 09:18:00 +02:00
441042bef4
yosys_nextpnr_toolchain: add flow3 option to abc9 mode
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Add "flow3" option to abc9 mode. This runs FPGA mapping several times,
producing a generally better mapping at the cost of increased runtime
(see https://github.com/Ravenslofty/yosys-cookbook/blob/master/ecp5.md ).
Also, add a "--yosys-flow3" build option to both "trellis" and "oxide".
Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
2022-09-18 08:28:40 -04:00
d7837f8751
demo: fix minor build issues
2022-09-17 19:05:45 -05:00
5b524485e8
increase jtaguart speed using large transfers in openocd
2022-09-17 17:57:18 -05:00
c24bbedb68
interconnect/axi/axi_full: Fix AXIUpConverter compilation.
2022-09-16 14:06:22 +02:00
1e1e75dba7
software/bios/boot: Fix missing CONFIG_BIOS_NO_DELAYS update.
2022-09-16 14:05:45 +02:00
fa902281aa
integration/common/get_mem_data: Allow filemane_or_regions to be None and add endianness assertion.
2022-09-16 14:05:20 +02:00
d36f98bf45
axi/axi_full: Simplify by switching AXI channels to AXIStreamInterface.
2022-09-15 15:52:03 +02:00
bc385c7358
interconnect/axi/axi_stream: Simplify by always adding id/dest/user to endpoints and add layout/name parameters for more flexibility.
2022-09-15 15:25:59 +02:00
3cd4a3830c
cores/dma/WishboneDMAWriter: Add ready_on_idle parameter and set it to 1 by default.
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This allows controlling ready behavior on idle state.
2022-09-14 10:02:07 +02:00
0adb604c97
Merge pull request #1423 from zyp/improve_dma
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Improve DMA
2022-09-14 09:57:43 +02:00
89bb688500
Merge pull request #1426 from enjoy-digital/naxriscv-merge
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cpu/NaxRiscv fix peripheral bus width to 32 bits and CLINT is now protected from overflow glitches
2022-09-12 23:25:47 +02:00
0a380b9c3b
cpu/NaxRiscv improve peripheral read/write speed by staying 32 bits
2022-09-12 19:19:35 +02:00
8e7fd9bc1f
Merge branch 'master' into naxriscv-merge
2022-09-12 19:18:12 +02:00
23f529a313
soc/builder: Propagate data_width to get_mem_data.
2022-09-12 16:46:20 +02:00
481234de91
integration/common/get_mem_data: Add data_width support.
2022-09-12 16:45:55 +02:00
a7cc1af416
soc: Propagate main bus address_width to the different interfaces dynamically created.
2022-09-12 16:13:45 +02:00
95bed6de5c
interconnect/wishbone: Allow passing address_width (In byte addressing).
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This is useful to abstract interfaces and propagate address_width.
Idealy, Wishbone should be fully switch to byte addressing since word addressing
has been a source of common issues/errors in the past but compatibility issues
would need to be evaluated first.
2022-09-12 16:12:52 +02:00
91c521a22a
Changes: Prepare for next release changes.
2022-09-12 11:08:50 +02:00
ded3bad178
cpu/naxriscv: Minor cleanups on recent changes.
2022-09-12 11:01:42 +02:00
f2a088bfcc
Merge pull request #1355 from cklarhorst/master
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integration/soc Add accessible_region to add_memory_buses
2022-09-12 10:18:22 +02:00
fa0c2df687
CHANGES: Update and release.
2022-09-12 09:00:36 +02:00
3c4c12a72f
cores/dma: End transfer when the last flag is set.
2022-09-10 10:15:37 +02:00
6ad6d1e414
cores/dma: Don’t drop data while idle.
2022-09-10 10:15:37 +02:00
6367fc6cab
update naxriscv comments
2022-09-09 13:19:36 +02:00
15f72174ce
interconnect/axi/axi_full: Add region signal to aw/ar and optional user signal to aw/w/b/ar/r channels.
2022-09-09 12:46:31 +02:00
14160ce7e3
cpu/NaxRiscv update nax with peripheral memory region
2022-09-09 11:23:24 +02:00
b7e2d24f37
interconnect/wishbone/DownConverter: Avoid FSM and Idle cycle.
2022-09-08 17:41:24 +02:00
a04f20880f
Change naxriscv memory-region format
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It now has a mode and a bus field.
modes: rwxc (read, write, execute, cachable)
bus: pm (peripheral, memory)
2022-09-08 17:33:20 +02:00
e5de4b356a
interconnect/axi/axi_lite: Add prot signal.
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Not directly used by LiteX but useful for wrapping AXI-Lite RTL code.
2022-09-08 12:06:35 +02:00
3b714c8145
test: Add minimal test_axi_stream test (Just syntax check for now).
2022-09-08 11:53:05 +02:00
afc89c9350
interconnect/axi/axi_stream: Add ID/Dest support and minor cleanup.
2022-09-08 11:51:55 +02:00
5b8d3651a9
software/liblitedram: Enable ECP5DDRPHY features on GW2DDRPHY (since very similar).
2022-09-07 16:27:54 +02:00
ee536f9cd5
CONTRIBUTORS: Update.
2022-09-07 10:13:17 +02:00
85e8aab5ae
tools/litex_contributors: Sort contributors by names.
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The git .csv generation is already sorted but this needs to be sorted again due
to the companies renaming.
2022-09-07 10:07:12 +02:00
0bd19fd026
tools/litex_contributors: Rename authors to contributors.
2022-09-07 09:49:26 +02:00
0144612751
tools/litex_contributors: Add RapidSilicon to companies.
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RapidSilicon is helping funding the improvement/development of LiteX features
and the team also contribute directly to the project.
2022-09-07 09:48:27 +02:00
4d6813ae64
tools/litex_contributors: Sort years.
2022-09-07 09:42:20 +02:00
a6acfb9a37
stream/Buffer: Integrate PipeValid/PipeReady (both configurable) and add tests.
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Allow selecting pipelining of valid/data or/and ready and creating a full Skid Buffer
(Pipeline of both valid/data and ready).
2022-09-07 08:59:37 +02:00
ce90181046
cpu/VexRiscv_SMP add --wishbone-force-32b option
2022-09-06 13:13:45 +02:00
af43e98e78
Merge branch 'naxriscv-merge'
2022-09-06 13:07:54 +02:00
5fad94f9d6
cpu/VexRiscv_SMP add --wishbone-force-32b option
2022-09-06 11:23:36 +02:00
36297c7a1e
cores/video: Avoid serializer_attrs.
2022-09-05 09:49:15 +02:00
Florent Kermarrec
Gabriel Somlo
Maciej Kurc
Gwenhael Goavec-Merou
Thomas Watson
Dolu1990
Vegard Storheil Eriksen
Christian Klarhorst