Commit Graph

9209 Commits

Author SHA1 Message Date
Florent Kermarrec faae1ea95a integration/soc/jtag: Switch JTAGPHY to sys_clk/simplify. 2023-12-13 09:24:23 +01:00
Florent Kermarrec 4e57cca85f cpu/vexriscv: Cleanup reset. 2023-12-13 09:17:15 +01:00
Florent Kermarrec f2c5ff376c soc/cores/jtag: Switch to stream.ClockDomainCrossing and use common_rst. 2023-12-13 09:16:55 +01:00
Gwenhael Goavec-Merou 94eca8628c Revert "soc/integration/soc: add_sdram, remove litedram_wb and converter: let LiteDRAMWishbone2Native dealing with addr/data width"
This reverts commit 6d34b8ed87.
2023-12-12 15:19:16 +01:00
Gwenhael Goavec-Merou 6d34b8ed87 soc/integration/soc: add_sdram, remove litedram_wb and converter: let LiteDRAMWishbone2Native dealing with addr/data width 2023-12-12 12:05:47 +01:00
Gwenhael Goavec-Merou 08ff003178 tools/litex_server.py: jtag/udp mode: add missing addr_width parameter 2023-12-09 06:08:53 +01:00
Gwenhael Goavec-Merou c1871eaf42 soc/integration/soc: add_jtagbone: pass address_width to UARTBone constructor 2023-12-09 06:07:58 +01:00
Florent Kermarrec acd66f1346 soc/bus_addressing_convert: Fix s2m adaptation case, the 2 adaptation cases were swapped. 2023-12-08 15:25:30 +01:00
Florent Kermarrec 8d6120c476 CHANGES: Update. 2023-12-08 12:11:37 +01:00
enjoy-digital 1e5df2dedf
Merge pull request #1851 from trabucayre/add_64_bus_support_v2
Add AXI/AXILite 64 bus support
2023-12-08 12:08:09 +01:00
Gwenhael Goavec-Merou 2134c0d0b0 soc/integration/soc: when adding a CSR Bridge bus_bridge must keep bus.address_width instead of the default value 2023-12-08 12:02:45 +01:00
Gwenhael Goavec-Merou 1a8fd2e808 soc/interconnect/axi/axi_full: AXIInterconnectShared, AXICrossbar: propagate master bus address width to Interface 2023-12-08 12:00:50 +01:00
Gwenhael Goavec-Merou 13987659a9 soc/interconnect/axi/axi_lite: AXILiteInterconnectShared, AXILiteCrossbar: propagate master bus address width to Interface 2023-12-08 11:59:33 +01:00
Gwenhael Goavec-Merou 01ce8ab0d1 soc/interconnect/axi/axi_lite:axi_lite_to_simple: avoid multiple read access 2023-12-08 11:57:35 +01:00
Florent Kermarrec afaeca98ce CHANGES.md: Update. 2023-12-07 16:33:32 +01:00
enjoy-digital 1512080527
Merge pull request #1850 from trabucayre/efinix_serdes
Efinix PLL calc when feedback != INTERNAL
2023-12-07 15:05:57 +01:00
Gwenhael Goavec-Merou 491a207a37 soc/cores/clock/efinix: calc PLL parameters for Trion when feedback != INTERNAL 2023-12-07 12:08:28 +01:00
Gwenhael Goavec-Merou 08a62d4b5f build/efinix/ifacewriter: PLL feedback for Trion 2023-12-06 16:58:50 +01:00
Gwenhael Goavec-Merou a4ead5cab9 litex/soc/integration/soc: SoCBusHandler 64bits address width support 2023-11-30 17:47:32 +01:00
Gwenhael Goavec-Merou fba581f77e build/efinix/ifacewriter: LVDS_RX/Trion: enable static rx delay when delay > 0 2023-11-30 17:46:55 +01:00
Florent Kermarrec cba58a0e36 tools/litex_client: Fix csr_data_width/csr_bus_address_width is None cases. 2023-11-23 16:30:29 +01:00
Florent Kermarrec 022776801a build/efinix/ifacewriter: Ident set_property in generate functions to make it more understandable (for the ones who like black magic... :) 2023-11-17 12:06:24 +01:00
enjoy-digital 16bbb8cdd2
Merge pull request #1843 from trabucayre/efinix_serdes
Efinix Trion serdes
2023-11-17 11:56:18 +01:00
Gwenhael Goavec-Merou fecc0cb227 build/efinix/ifacewriter: PLL/LVDS serdes: Trion support 2023-11-17 11:50:58 +01:00
Gwenhael Goavec-Merou cbba5b46e9 build/efinix/efinity: fix 90 phase shift float -> int (yes: WHY?) 2023-11-17 11:41:00 +01:00
Gwenhael Goavec-Merou c8a9f205e0 soc/cores/clock/efinix: allowing to specify LVDS input refclk name (Trion) 2023-11-17 11:40:41 +01:00
Florent Kermarrec 4353135f02 CHANGES: Update. 2023-11-16 13:47:17 +01:00
Florent Kermarrec aa8e9dc32f integration/builder: Add bios_format/--bios-format support to allow selecting printf format and pass it to picolibc.
Useful to printf of float/double is required.
2023-11-16 12:38:59 +01:00
Dolu1990 6d9cacd465 core/NaxRiscv update (timing improvements) 2023-11-14 13:45:01 +01:00
Gwenhael Goavec-Merou f41ae88d1c soc/cores/clock/efinix: create_clkin: adding lvds_input optional parameter (required when used with LVDS serdes) 2023-11-14 11:34:13 +01:00
Gwenhael Goavec-Merou 7cee8e10fd build/efinix/ifacewriter: allowing PLL to have LVDS_RX as input type 2023-11-14 11:24:17 +01:00
Gwenhael Goavec-Merou 232941be24 build/efinix/ifacewriter: generate_lvds: adding missing migen import (required by generate_lvds) 2023-11-14 11:14:57 +01:00
Gwenhael Goavec-Merou bf337559fe build/efinix/ifacewriter: generate_lvds: adding LVDS serdes support (Titanium only) 2023-11-14 10:45:16 +01:00
Florent Kermarrec edc6871ace soc/software: Rename NR_IRQ to CONFIG_CPU_INTERRUPTS. 2023-11-13 09:14:57 +01:00
Florent Kermarrec d7253ffd0e integration/soc/add_etherbone: Rename ethernet parameter to with_ethmac and minor cosmetic cleanups. 2023-11-13 08:57:22 +01:00
enjoy-digital 2d9a268ff3
Merge pull request #1838 from motec-research/etherbone
Hybrid Etherbone simplification
2023-11-13 08:48:29 +01:00
Gwenhael Goavec-Merou a18537bf50 build/gowin/common: disable Tristate (uncorrect code with tangNano9k hypperram #1833) 2023-11-13 06:34:59 +01:00
AndrewD 968bd28d8b
Merge pull request #1815 from motec-research/irq_attach
soc/software: add irq_attach() / irq_detach()
2023-11-13 14:30:48 +11:00
Andrew Dennison 737ced8fa6 soc/software: add irq_attach() / irq_detach()
cleaner mechanism for other software to use interrupts
2023-11-13 12:07:35 +11:00
Andrew Dennison 885d5b9cb1 tools/litex_sim: update hybrid etherbone integration 2023-11-13 11:13:19 +11:00
Andrew Dennison fb5512f6d5 soc/integration/soc: simplify hybrid etherbone 2023-11-13 11:13:10 +11:00
Florent Kermarrec 77ca872b3b tools/litex_sim: Update Etherbone/Ethernet hybrid mode integration. 2023-11-10 19:13:35 +01:00
Florent Kermarrec 57782309a2 integration/soc/add_etherbone: Exclude MAC from CSRs when in hybrid board since added externally. 2023-11-10 18:59:28 +01:00
Florent Kermarrec 9f88137ab6 remote/etherbone: Set default addr_size of 32 (To avoid breaking old code). 2023-11-10 16:13:43 +01:00
Florent Kermarrec 52adf240f9 remote/etherbone/EtherbonePacket: Set default addr_width of 32 (To avoid breaking old code using EtherbonePacket()). 2023-11-10 13:17:21 +01:00
Florent Kermarrec 5672a9dd2a CONTRIBUTORS: Update. 2023-11-10 10:35:49 +01:00
Florent Kermarrec 639c899838 CHANGES.md: Update. 2023-11-10 10:27:37 +01:00
Florent Kermarrec c419706856 CHANGES: Update. 2023-11-09 15:24:40 +01:00
Florent Kermarrec 9b4df14ab1 build/gowin/common/GowinTristate: Remove print. 2023-11-09 14:55:46 +01:00
Florent Kermarrec 48a1b2634c cores/video/VideoHDMIPHY: Fix when multiple drive_pols. 2023-11-09 13:45:27 +01:00