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Dolu1990-patch-1

Dolu1990-patch-2

Dolu1990-patch-3

allows_clk_name_override

ci-cpus

ci-cva6

ci-dev-test

ci-openrisc

ctu-can-fd

dma_nax

efinix_fixes

efinix_fixes2

efinix_iface_signal_names

export_csr_c_rework

framebuffer_change

generic_toolchain

ghdl_fix

gowin_emcu_uart

hyperbus_2x

hyperbus_io_regs

hyperbus_variable_latency

hyperram_decoupling

hyperram_new

kianv

liteeth_wishbone_tx_rx_buses

master

multi-channel-pwm

naxriscv-merge

naxriscv_update

neorv32_litex_wrapper

neorv32_params

urv

usb_ohci_phy_fix

verilog_improvements

verilog_improvements_2

vexriscv_smp_irqs

video_framebuffer_skip_first_frame

video_mod_fix

wishbone_dma_ctrl

wishbone_word_byte_addressing

wuff

zynqmp_aximaster_eth_i2c_uart

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89d2b67539

Merge 73f493a5c4 into a899c23f65 JoyBed 2024-06-17 13:59:40 +0200
a899c23f65 soc/interconnect/packet: Add default values for HeaderField parameters. Florent Kermarrec 2024-06-17 10:54:53 +0200
73f493a5c4

Forgot to also specify version in GP master JoyBed 2024-06-16 19:00:43 +0200
73e0d15da0

Merge pull request #1 from JoyBed/patch-2 JoyBed 2024-06-16 18:57:24 +0200
45aa347e9a

Add connect_mapped function JoyBed 2024-06-16 18:53:58 +0200
0bea7cb005

Fix HP slave clock source and specify AXI version JoyBed 2024-06-16 18:50:55 +0200
81b70d1e37 soc/integration/builder: Only generate svd/memory.x export when specified (Since often not required and generation does not seems robust to all designs). Florent Kermarrec 2024-06-14 14:58:06 +0200
69008d7d5e software/libbase/isr.c: Fix regression. Florent Kermarrec 2024-06-14 14:08:22 +0200
8278ff6622 software/libbase/isr.c: Generalize irq_table/attach/detach to all CPUS to have a common approach. Florent Kermarrec 2024-06-14 12:08:52 +0200
45753a3cc2 software/libbase/isr.c: Move ISR handling in more logical order (RISC-V PLIC first). Florent Kermarrec 2024-06-14 11:49:26 +0200
38e060c354 software/libbase/isr.c: Cleanup code a bit. Florent Kermarrec 2024-06-14 11:47:02 +0200
6164a55c6b cpu/cva6: Switch to common PLIC handling code to make it similar to other PLIC based CPU and avoid code "duplication". Florent Kermarrec 2024-06-14 11:26:43 +0200
b58186a99d build/vhd2v_converter: Add GHDL synth woraround. Florent Kermarrec 2024-06-14 11:25:21 +0200
28d4aff10f vexii non coherent config write bandwidth improvment Dolu1990 2024-06-13 23:20:25 +0200
3fa3532f16 cores/video: Add fifo_depth parameter to add_video_framebuffer and use new KILOBYTE to define depth. Florent Kermarrec 2024-06-13 12:59:09 +0200
491974c719 litex_json2dts_linux: Cleanup bootargs IP address generation. Florent Kermarrec 2024-06-13 12:14:44 +0200
02d6e9760a litex_json2dts_linux: Improve/rework RISC-V cpu_isa_base/cpu_isa_extentions and make it specific to RISC-V CPUs. Florent Kermarrec 2024-06-13 11:55:54 +0200
3e756ecbbe CHANGES.md: Update. Florent Kermarrec 2024-06-13 10:15:22 +0200
fcf9b3b335 litex_json2dts_linux: Use new byte size definition from litex.gen.common. Florent Kermarrec 2024-06-13 09:55:19 +0200
d782a0f8c6 litex/gen/common: Add short and long byte size definitions. Florent Kermarrec 2024-06-13 09:54:06 +0200
abdf6d3ee7 soc/integration: Generate CPU_FAMILY config and use it to simplify litex_json2dts_linux.py. Florent Kermarrec 2024-06-13 09:33:04 +0200
962bd67431 litex_json2dts_linux: Rename ncpus to cpu_count (Consistency with other variables). Florent Kermarrec 2024-06-13 09:12:41 +0200
2ddf9bb4e5

Merge pull request #1985 from VOGL-electronic/add_spi_master enjoy-digital 2024-06-13 09:01:48 +0200
7306c3862e

Merge pull request #1984 from VOGL-electronic/json2renode_elf enjoy-digital 2024-06-13 09:00:25 +0200
2e4813d6ae Fix vexii axi3 Dolu1990 2024-06-12 19:33:20 +0200
eb3aca2a46 build/vhd2v_converter: Make instance rename when multiple instance more robust. Florent Kermarrec 2024-06-12 15:16:03 +0200
8d8dd117b6 soc/integration/builder: Now generates exports by default to output_dir with default name unless explicitly specified. Florent Kermarrec 2024-06-12 11:44:34 +0200
8bb10e1617 cpu/vexii: Add AXI3 support via --with-axi3 Dolu1990 2024-06-12 11:25:18 +0200
6ed61e11bc

Merge pull request #1983 from Dolu1990/vexiiriscv Gwenhael Goavec-Merou 2024-06-11 18:40:13 +0200
8c80a6c19c linux dts: rework "rocket" in cpu_name into cpu_name == "rocket" Dolu1990 2024-06-11 13:08:25 +0200
bb155b5a90 litex_json2dts_zephyr.py: add custon handler for spiflash Fin Maaß 2024-05-29 11:57:18 +0200
44b6fb5a28 add spi master function Fin Maaß 2024-05-29 11:51:24 +0200
53ae12ca65 litex_json2renode: correct VexRiscv variants Fin Maaß 2024-06-11 10:40:06 +0200
1ee2e3a31d litex_json2renode: add option for elf bios Fin Maaß 2024-06-11 10:36:30 +0200
87ae5db16b linux dts: add vexii clint support Dolu1990 2024-06-10 18:10:13 +0200
f0b0d8db29 linux dts: add vexii clint support Dolu1990 2024-06-10 17:01:40 +0200
4e044f54c7 CHANGES: Update. Florent Kermarrec 2024-06-08 15:39:33 +0200
7f81499cc5

Merge pull request #1923 from Dolu1990/vexiiriscv enjoy-digital 2024-06-08 15:37:37 +0200
9167d053cc CHANGES.md: Prepare for post 2024.04 changes. Florent Kermarrec 2024-06-08 15:22:11 +0200
9c202b59d1 Fix axi id width Dolu1990 2024-06-07 18:33:05 +0200
bd96b47041 Vexii fix mem data width Dolu1990 2024-06-06 16:36:56 +0200
e25de0f499 build/vhd2v_converter.py: pass work_package to platform Gwenhael Goavec-Merou 2024-06-06 15:24:20 +0200
0e04949485 vexii fix l1 cache size Dolu1990 2024-06-06 13:50:27 +0200
b2b7130b7b version: Bump to 2024.04. 2024.04 Florent Kermarrec 2024-06-05 22:09:48 +0200
9190f581e4 soc/integration/builder: use output_dir for csr Andrew Dennison 2024-02-06 11:24:04 +1100
abcc0b8ab6 Fix EOS-S3 build on F4PGA Artur Kowalski 2023-10-11 18:42:20 +0200
329bd36f7f tools/litex_json2dts_linux: Update. Florent Kermarrec 2024-05-30 12:07:54 +0200
b31114bd50 CHANGES.md: updated for microsemi/microchip libero_soc toolchain Gwenhael Goavec-Merou 2024-05-30 09:35:51 +0200
cc1a37e386 soc/intergration: Define platform/identifier as configs (and change PLATFORM to PLATFORM_NAME). Florent Kermarrec 2024-05-30 09:28:34 +0200
72854b8bef soc/integration/soc: Move adding constant for identifier directly to add_identifier method. Florent Kermarrec 2024-05-30 09:19:24 +0200
d9332da433

Merge pull request #1973 from motec-research/dts_schema_compliance enjoy-digital 2024-05-30 09:16:01 +0200
f8cee3836d

Merge pull request #1972 from motec-research/dts_all_soc_sys_clk enjoy-digital 2024-05-30 09:14:11 +0200
03e0f0d9a8 build/microsemi/libero_soc.py: replaced tabs by spaces Gwenhael Goavec-Merou 2024-05-30 08:57:59 +0200
72cade55da

Applying updates for Libero SoC support (#1855) CLappin 2024-05-30 07:56:27 +0100
94e6bb0247 CHANGES.md: updated for eos_s3 and quicklogic f4pga toolchain Gwenhael Goavec-Merou 2024-05-30 08:46:42 +0200
845e20c653 build/quicklogic/f4pga.py: fix Makefile, added a note for futur rework and link to toolchain install's instructions Gwenhael Goavec-Merou 2024-05-30 08:43:41 +0200
5e0c3f0a04 tools/litex_json2dts_linux: add compatible, model Andrew Dennison 2024-05-21 10:37:42 +1000
ddc521b033 tools/litex_json2dts_linux: fix tlb-split Andrew Dennison 2024-05-21 10:05:06 +1000
8a0d50b03e tools/litex_json2dts_linux: add all soc sys_clk Andrew Dennison 2024-05-17 09:46:23 +1000
d79c91daea

Merge pull request #1797 from Dasharo/s3_fix Gwenhael Goavec-Merou 2024-05-30 06:24:14 +0200
a38c99f3db efinix: add synthesis options to a dictionary in the EfinityToolchain Joshua Wise 2024-05-29 19:11:10 -0400
23e654db4c

Merge pull request #1968 from VOGL-electronic/fix_liblitespi enjoy-digital 2024-05-28 15:43:07 +0200
7a3b3dcfa2

Merge pull request #1966 from maass-hamburg/dts_zepyhr_include_cpu enjoy-digital 2024-05-28 15:42:38 +0200
914167cb75

Merge pull request #1969 from enjoy-digital/ghdl_fix enjoy-digital 2024-05-28 15:20:43 +0200
5257ddaac0 ci: Build/Install GHDL from sources. ghdl_fix Florent Kermarrec 2024-05-28 13:57:28 +0200
9165886525 snyc Dolu1990 2024-05-28 12:59:27 +0200
025149c6c5 liblitespi: Fix #1967 Matthias Breithaupt 2024-05-28 09:38:59 +0200
2dac84f32c vexii l2 now support self flush. ex : --l2-self-flush=40c00000,40DD4C00,1666666 Dolu1990 2024-05-27 17:37:30 +0200
ae13f159c4 litex_json2dts_zephyr.py: include cpu Fin Maaß 2024-05-27 11:26:55 +0200
47bab2fcff CHANGES.md: Update. Florent Kermarrec 2024-05-27 08:41:58 +0200
2235c711e6

Merge pull request #1964 from acceleratedtech/jwise/output-load-trion enjoy-digital 2024-05-27 08:40:49 +0200
aa9ad61674

Merge pull request #1962 from VOGL-electronic/master enjoy-digital 2024-05-27 08:36:40 +0200
7ad3f2ce34 efinix: be able to specify TX_OUTPUT_LOAD on a LVDS PHY on Trion Joshua Wise 2024-05-24 18:10:24 -0400
eed89ba3a3 Add support for the Efinix reconfiguration interface Matthias Breithaupt 2024-05-23 11:48:48 +0000
4a6efa47c1 Add variants to VexiiRiscv Dolu1990 2024-05-23 16:44:20 +0200
56371c4d9f

Merge pull request #1961 from maass-hamburg/dts_zephyr_include_ctrl enjoy-digital 2024-05-23 15:52:24 +0200
77683f1659 litex_json2dts_zephyr.py: include ctrl Fin Maaß 2024-05-22 16:16:03 +0200
0af1ae8c64 soc/cores/cpu/zynqmp/core.py: added add_gpios method to connect EMIO to the PSU's GPIO controler Gwenhael Goavec-Merou 2024-05-22 15:55:46 +0200
44d049f3ad litex/soc/integration/soc.py: add_uart: disable check_duplicate -> required when this method is called more than once Gwenhael Goavec-Merou 2024-05-22 15:53:52 +0200
14dbdeb0cb soc/integration/export: Disable fields_access_function by default. Florent Kermarrec 2024-05-21 10:24:37 +0200
05030990b2 soc/integration/export: Add LITEX_CSR_ACCESS_FUNCTIONS/LITEX_CSR_FIELDS_ACCESS_FUNCTIONS defines to allow user to disable access functions. Florent Kermarrec 2024-05-21 10:17:13 +0200
5b297f5601 soc/integration_export: Split C header generation by sections. Florent Kermarrec 2024-05-21 09:58:05 +0200
4502edd33e soc/integration/export: Prepare split of C header generation in sections. Florent Kermarrec 2024-05-21 09:15:21 +0200
a47bbb28f5 uartbone+crossover: add dynamic mux so that programs can boot into full-bandwidth UART, but enable debuggability as needed Joshua Wise 2024-05-20 22:05:14 -0400
06bbbe78e4 vexii/naxii fix floating axi wires Dolu1990 2024-05-20 08:56:38 +0200
21e0ec7f98 vexii/naxii fix floating axi wires Dolu1990 2024-05-20 08:55:05 +0200
10083f4d87

Merge pull request #1958 from nrndda/patch-1 Gwenhael Goavec-Merou 2024-05-18 21:33:25 +0200
2d52c65613

Simple mistake fix Dmitry 2024-05-18 19:09:13 +0000
5eeb999694 update vexii Dolu1990 2024-05-18 16:59:27 +0200
8c0f5447ed fix nax/vexii git checkout process, thanks JoyBed Dolu1990 2024-05-18 10:01:29 +0200
4b3f147fc8 CHANGES: Update. Florent Kermarrec 2024-05-17 12:57:29 +0200
d5f9d57c2b

Merge pull request #1956 from enjoy-digital/zynqmp_aximaster_eth_i2c_uart enjoy-digital 2024-05-17 12:54:06 +0200
943c0c263d soc/cores/cpu/zynqmp/core.py: added method to enable ZynqMP UART interface in EMIO mode zynqmp_aximaster_eth_i2c_uart Gwenhael Goavec-Merou 2024-05-17 11:02:41 +0200
49488e5e01 soc/cores/cpu/zynqmp/core.py: added method to enable ZynqMP i2c interface in EMIO mode Gwenhael Goavec-Merou 2024-05-17 11:02:31 +0200
e95edaf9be soc/cores/cpu/zynqmp/core.py: added method to enable ZynqMP ethernet interface in EMIO mode (with gmii_to_rgmii) Gwenhael Goavec-Merou 2024-05-17 11:02:16 +0200
1986b79b9a soc/cores/cpu/zynqmp/core.py: add_axi_gp_master: removed loop over layout to have a more clear / easy to maintain connexion Gwenhael Goavec-Merou 2024-05-17 11:02:02 +0200
c5592ca8da soc/cores/cpu/zynqmp/core.py: allows user to specify default configuration (preset) with a tcl file Gwenhael Goavec-Merou 2024-05-17 11:01:46 +0200
0720ffb404 Update vexii Dolu1990 2024-05-17 10:00:24 +0200
882463d9db

Merge pull request #1955 from Dolu1990/nax64_irq enjoy-digital 2024-05-17 08:20:46 +0200
122e060a5e update vexii Dolu1990 2024-05-16 19:30:15 +0200