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picorv32
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313 Commits 2 Branches 1 Tag 2.8 MiB
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100 Commits

Author SHA1 Message Date
Clifford Wolf 5bea3f9917 Added more asserts for the memory interface 2016-09-13 19:34:14 +02:00
Clifford Wolf 2f3e3a6910 Merge pull request #21 from wallclimber21/mem_wdata 
Only clock mem_wdata when necesssary
 2016-09-08 09:42:51 +02:00
Tom Verbeure 38a760daf8 Fix tabs 2016-09-07 20:34:28 -07:00
Tom Verbeure 80aa70ec2e Only clock mem_wdata when necessary 2016-09-07 20:32:32 -07:00
Clifford Wolf 44d6feba2a Using assertpmux in "make check" 2016-09-07 12:40:19 +02:00
Clifford Wolf da37498191 Two minor bugfixes 2016-09-06 19:58:03 +02:00
Clifford Wolf 7f946d0f84 Added misisng MUL_CLKGATE stage 2016-09-06 01:02:12 +02:00
Clifford Wolf 5fdee952c9 Added picorv32_pcpi_fast_mul MUL_CLKGATE 2016-09-05 22:37:52 +02:00
Clifford Wolf e45cc362a7 More picorv32_pcpi_mul timing improvements 2016-09-04 18:34:11 +02:00
Clifford Wolf e91c1422a2 Added optional FFs to picorv32_pcpi_fast_mul 2016-09-04 12:44:12 +02:00
Clifford Wolf d5b7e9e175 Minor bugfix/cleanup (mostly for formal verification) 2016-09-03 14:40:13 +02:00
Clifford Wolf c9519df01b Moved cpuregs read/write to extra always blocks 2016-08-31 11:50:07 +02:00
Clifford Wolf 82d837bf96 Be more explicit about single register file write port 2016-08-31 00:08:33 +02:00
Clifford Wolf bfba9b3eb3 Bugfix in picorv32_pcpi_fast_mul 2016-08-30 11:14:46 +02:00
Clifford Wolf b9ed4364d4 Merge branch 'fast_mul_opt' of https://github.com/wallclimber21/picorv32 2016-08-30 11:12:42 +02:00
Clifford Wolf cefe09b8d4 Minor fixes/cleanups in mul reset logic 2016-08-30 11:12:16 +02:00
Tom Verbeure 9201bff2ef Reduce rs1, rs2 from 64 to 33 bits to make life for synthesis tools easier. 2016-08-29 18:00:49 -07:00
Clifford Wolf a6210c06d4 Added picorv32_pcpi_fast_mul core 2016-08-29 23:38:05 +02:00
Clifford Wolf 90070736d6 More asserts 2016-08-29 22:44:15 +02:00
Clifford Wolf 28fe45ffe9 Added more asserts to picorv32, more smtbmc examples 2016-08-29 17:23:00 +02:00
Clifford Wolf 72158ba4a5 Some minor cleanups 2016-08-26 23:56:04 +02:00
Clifford Wolf d1d3c3c5e1 Added next gen yosys-smtbmc verification scripts 2016-08-26 23:39:39 +02:00
Clifford Wolf 98d248d2c2 Finalized tracer support 2016-08-26 14:54:27 +02:00
Clifford Wolf 7094e61af7 Added tracer support (under construction) 2016-08-25 14:15:42 +02:00
Clifford Wolf 8043c90a04 Added REGS_INIT_ZERO parameter 2016-08-24 15:20:23 +02:00
Clifford Wolf 288a043aca Fixed use-before-declaration problem with VCS 2016-06-09 11:57:23 +02:00
Clifford Wolf bf062e39ac Added STACKADDR parameter 2016-06-07 17:05:02 +02:00
Clifford Wolf f4bb91b060 RISC-V ISA 2.1 now calls "sbreak" officially "ebreak" 2016-06-06 10:46:52 +02:00
Clifford Wolf 490a734519 Encode in q0 LSB if interrupted instruction is compressed 2016-06-01 12:39:00 +02:00
Clifford Wolf fd18475e23 Do not wait for PCPI core when handling SCALL and SBREAK 2016-06-01 11:57:04 +02:00
Steve Kerrison 38d51a3383 Deassert pcpi_valid upon asserting sbreak IRQ 
This fixes #8
 2016-05-31 19:54:16 +01:00
Clifford Wolf 63c28e4389 Update dbg_ signals synchronous to the actual launch of the new insn 2016-04-14 00:50:18 +02:00
Clifford Wolf fb3178c4b7 Fixed dbg_ signals: no latches (formal verification doesn't like latches) 2016-04-13 17:29:33 +02:00
Clifford Wolf 436f162951 Minor change in DEBUGASM output 2016-04-13 15:30:02 +02:00
Clifford Wolf faa1c1a159 Added SBREAK handling for CATCH_ILLINSN=0 2016-04-13 15:09:49 +02:00
Clifford Wolf 262a9085bb Streamlined debug signals 2016-04-13 13:49:40 +02:00
Clifford Wolf 49aef71641 Some area improvements 2016-04-13 12:27:00 +02:00
Clifford Wolf 435232eb85 Use ifdef instead of generate if so we don't confuse Vivado 2016-04-13 12:21:47 +02:00
Clifford Wolf 2c76f7d61b Added (by default disabled) register file access wires for debugging 2016-04-12 20:55:46 +02:00
Clifford Wolf 789a411ead Bugfix for CATCH_ILLINSN <-> WITH_PCPI interaction 2016-04-12 20:55:06 +02:00
Clifford Wolf e9c7ea6b5d Added ENABLE_COUNTERS64 config parameter 2016-04-12 18:04:16 +02:00
Clifford Wolf 2fdafb9c16 Added BARREL_SHIFTER config parameter 2016-04-12 17:30:31 +02:00
Clifford Wolf b41c0e723c Do not re-load a word to read the 16 bit opcode in the upper half 2016-04-11 16:48:57 +02:00
Clifford Wolf b08d9400bd Do not load next word when loading a 16 bit opcode from the upper half of a 32bit word 2016-04-11 14:32:25 +02:00
Clifford Wolf 2cab981862 Fixed signed division by zero handling 2016-04-10 17:15:17 +02:00
Clifford Wolf 00dd6ac38e Added ENABLE_DIV and picorv32_pcpi_div 2016-04-10 16:54:35 +02:00
Clifford Wolf fce9656604 Bugfix in memory interface (related to compressed ISA) 2016-04-10 13:25:28 +02:00
Clifford Wolf aa17d58784 Bugfix in C.SRAI implementation 2016-04-09 14:27:28 +02:00
Clifford Wolf ef8014eebd Bugfix in C.ADDI4SPN implementation 2016-04-09 14:09:43 +02:00
Clifford Wolf d7894ca41a Merge branch 'master' into compressed 
Conflicts:
	picorv32.v
 2016-02-03 16:21:53 +01:00