Hardware
/
VexRiscv
mirror of https://github.com/SpinalHDL/VexRiscv.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity
232 Commits 39 Branches 2 Tags 15 MiB
Commit Graph

232 Commits

Author SHA1 Message Date
Dolu1990 04ca72df66
Update README.md 2017-12-05 16:29:26 +01:00
Dolu1990 f10dabd253 SpinalHDL 0.11.5 update 2017-12-05 15:58:05 +01:00
Dolu1990 e1b86ea511 SpinalHDL 0.11.4 update 2017-12-01 11:19:23 +01:00
Dolu1990 586d3ed286 Update formal VexRiscv to halt on missaligned dbus 2017-11-26 15:30:48 +01:00
Dolu1990 4de0aac469 Merge branch 'formal' 2017-11-24 14:03:25 +01:00
Dolu1990 b7f4f09814 Update verilator makefiles to support the last SpinalHDL changes (process merges) 2017-11-21 23:56:46 +01:00
Dolu1990 9b9bbaa4ad Add missing full config for the iBus 2017-11-21 00:09:02 +01:00
Dolu1990 ce6fd6d0aa Add VexRiscvAxi4 demo 2017-11-20 23:57:37 +01:00
Dolu1990 7c19288648 Update Synthesis bench 
Update some synthesis results
 2017-11-17 20:10:46 +01:00
Dolu1990 635417aec2
Merge pull request #9 from kaofishy/master 
Minor fixes to Murax.scala
 2017-11-16 21:16:53 +01:00
Tony Kao 290dbc106e Fixes GPIO width mismatch 
Adds explicit type to apbDecoder.slave to suppress IDE errors
 2017-11-16 15:02:13 -05:00
Dolu1990 9f9ec823b8 SpinalHDL 0.11.2 2017-11-15 17:57:08 +01:00
Dolu1990 6c3fed3505 SpinalHDL 0.11.1 2017-11-15 16:44:42 +01:00
Dolu1990 be3d301eaf Merge remote-tracking branch 'origin/spinalhdl_reworkDev' 2017-11-12 13:08:05 +01:00
Dolu1990 838c13d68b spinal.core.internals literals import 2017-11-10 13:14:30 +01:00
Dolu1990 3060296b94 unsetRegIfNoAssignement -> allowUnsetRegToAvoidLatch 2017-11-10 11:33:04 +01:00
Dolu1990 c3a7f4e58c CSR unsetRegIfNoAssignement fix 
BranchPlugin doesn't emit the prediction cache when the STATIC setup is used
 2017-11-10 00:59:31 +01:00
Dolu1990 d6777ae8ec usetRegIfNoAssign upgrade 2017-11-09 20:10:56 +01:00
Dolu1990 a72c7fd0d1 Clean Murax toplevel by extracting integrated Area into dedicated components located in MuraxUtiles.scala 2017-11-07 22:19:33 +01:00
Dolu1990 714d44d248 Add fixed bug into the FormalPlugin comments 2017-11-07 13:54:07 +01:00
Dolu1990 0cf278b04f
Update README.md 2017-11-07 00:12:58 +01:00
Dolu1990 200a73bea0 Fix FormalPlugin to pass liveness again. 2017-11-06 23:04:33 +01:00
Dolu1990 8098a03a9b with no bus stall, pass all tests except uniqueness 2017-11-06 20:26:45 +01:00
Dolu1990 e2a432eb5e add HaltOnExceptionPlugin 
wip
 2017-11-05 20:13:27 +01:00
Dolu1990 276f7895e7 Add FormalPlugin 
Add FormalSimple CPU configuration
 2017-11-04 00:55:32 +01:00
Dolu1990 ba42f71813 pass VexRiscv regressions 2017-10-30 14:29:25 +01:00
Dolu1990 173336af33 Update README.md 2017-10-20 14:44:31 +02:00
Dolu1990 9d75349d7a Merge pull request #6 from plex1/master 
updated main.cpp
 2017-10-18 00:17:49 +02:00
Ubuntu 008a5b7309 updated main.cpp 
added missing using namespace std
 2017-10-17 22:09:08 +00:00
Dolu1990 228623a309 Update pinsec picture 2017-10-16 12:06:24 +02:00
Dolu1990 6f0c792cb8 Add brieySoc.png image 2017-10-16 12:02:40 +02:00
Dolu1990 2bf7ca24f2 Add VexRiscvAvalonWithIntegratedJtag 2017-10-16 11:52:17 +02:00
Dolu1990 8857bcd7f6 Add documentation about resets 2017-10-16 11:31:03 +02:00
Dolu1990 aa859aae6b Update framework.h 
Add missing using namespace std;
 2017-10-05 10:08:09 +02:00
Dolu1990 0327c5ec3a Update README.md 2017-08-31 10:09:11 +02:00
Dolu1990 09ba7c28da Change some xx.input(REGFILE_WRITE_DATA) for xx.output(REGFILE_WRITE_DATA) 2017-08-27 15:21:44 +02:00
Dolu1990 8168c9bf3a Update simd_add makefile 2017-08-27 14:49:36 +02:00
Dolu1990 a8191b6092 Fix sbt version to 0.13.7 2017-08-17 03:39:52 +02:00
Dolu1990 d543325294 script about gcc prebuild version 2017-08-17 02:46:12 +02:00
Dolu1990 3db3795e0a Update sbteclipse-plugin 2017-08-17 02:04:25 +02:00
Charles Papon 7811d90f99 update gcc path 2017-08-14 12:16:40 +02:00
Charles Papon 8fbd777794 Update readme with GCC changes from the VexRiscvSocSoftware repo 2017-08-14 11:40:33 +02:00
Charles Papon 85fa3776d3 Readme fix typo 2017-08-11 13:49:27 +02:00
Charles Papon 2c6889e688 Murax mainBus now handle unmapped memory access allowing the debug to access unmapped area without locking the CPU 
Murax add dhrystone config
 2017-08-10 22:48:00 +02:00
Dolu1990 6072e9157e Update VexRiscv area/Fmax 2017-08-10 22:13:19 +02:00
Charles Papon aa477b2b1c DebugPlugin now prevent the CPU catching exception when debug instruction are pushed 
Fix DataCache locking when loading mem read rsp  transaction has the flag set
Briey : Now the debug module reset the whole AXI system instead of only the CPU
Now in debug, you can access unmapped memory without crashing the CPU
 2017-08-10 20:56:54 +02:00
Charles Papon 37f2674d5b Add commands to genreate the SIMD_ADD cpu 2017-08-08 18:44:32 +02:00
Charles Papon 1653548140 Better readme about custum instruction testing 2017-08-08 18:36:23 +02:00
Charles Papon 54b06e6438 Add SIMD_ADD regression and config (show case) 2017-08-08 18:19:02 +02:00
Charles Papon 3307d6c3b5 Briey move CPU and UART generics from to toplevel to the toplevel configuration object 2017-08-06 15:42:37 +02:00