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VexRiscv
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240 Commits

Author SHA1 Message Date
Charles Papon 85fa3776d3 Readme fix typo 2017-08-11 13:49:27 +02:00
Charles Papon 2c6889e688 Murax mainBus now handle unmapped memory access allowing the debug to access unmapped area without locking the CPU 
Murax add dhrystone config
 2017-08-10 22:48:00 +02:00
Dolu1990 6072e9157e Update VexRiscv area/Fmax 2017-08-10 22:13:19 +02:00
Charles Papon aa477b2b1c DebugPlugin now prevent the CPU catching exception when debug instruction are pushed 
Fix DataCache locking when loading mem read rsp  transaction has the flag set
Briey : Now the debug module reset the whole AXI system instead of only the CPU
Now in debug, you can access unmapped memory without crashing the CPU
 2017-08-10 20:56:54 +02:00
Charles Papon 37f2674d5b Add commands to genreate the SIMD_ADD cpu 2017-08-08 18:44:32 +02:00
Charles Papon 1653548140 Better readme about custum instruction testing 2017-08-08 18:36:23 +02:00
Charles Papon 54b06e6438 Add SIMD_ADD regression and config (show case) 2017-08-08 18:19:02 +02:00
Charles Papon 3307d6c3b5 Briey move CPU and UART generics from to toplevel to the toplevel configuration object 2017-08-06 15:42:37 +02:00
Charles Papon 665df18ee9 Add version information about verilator on readme 2017-08-05 19:14:08 +02:00
Charles Papon 671aa5050e Move CPU and UART configs into the murax configuration object (in place of toplevel hardcoding) 
Add MuraxConfig.fast
 2017-08-04 14:55:54 +02:00
Charles Papon 9f65a21f3e Readme add information about the Murax with a demo program in ROM 2017-08-04 00:17:29 +02:00
Charles Papon c033b32fc9 scripts/murax remove jtag pullup which apparently break the functionality 2017-08-03 23:59:48 +02:00
Charles Papon d962406b26 scripts/murax better makefile, add pullup on jtag interface 2017-08-03 23:22:57 +02:00
Charles Papon ac59eebb8d Add Murax configuration which integrate a boot programme : 
Will blink led and echo UART RX to UART TX   (in the verilator sim, type some text and press enter to send UART frame to the Murax RX pin)
 2017-08-03 21:58:23 +02:00
Dolu1990 58981c0e8e Add Murax fast in synthesis bench 2017-08-01 21:14:09 +02:00
Charles Papon a37494f27f Set sbt organization to com.github.spinalhdl 2017-08-01 20:43:15 +02:00
Charles Papon a4d99d734b Typo fix 2017-08-01 00:01:52 +02:00
Charles Papon e3411012d7 Add links to demo software 2017-08-01 00:01:27 +02:00
Charles Papon f44b345132 Add console TX in the Murax verilator 2017-07-31 21:04:41 +02:00
Charles Papon fded0e7947 Add MIT license 2017-07-31 20:45:06 +02:00
Charles Papon 0c9a39d3ce Connect the UART interruption to the CPU 2017-07-31 17:20:47 +02:00
Charles Papon 568c7d1365 Update murax readme 2017-07-31 13:57:34 +02:00
Charles Papon c16a53c388 Refractoring of some arbitration signals 
Add UART into Murax
 2017-07-31 13:34:25 +02:00
Dolu1990 8708d2482f Add more information about dependencies 2017-07-30 11:37:22 +02:00
Charles Papon de33128e01 Add Murax 0.55 DMIPS/Mhz 2017-07-30 02:42:14 +02:00
Charles Papon 087e3dda89 Add Murax scripts 2017-07-29 22:43:43 +02:00
Charles Papon 2736681be6 Add Murax in the readme 2017-07-29 22:25:28 +02:00
Charles Papon e8aa828744 PcPlugin change fastPcCalculation into relaxedPcCalculation 
relaxedPcCalculation relax timings on the IBusSimple address => better FMax when the CPU is integrated into a SoC
 2017-07-29 21:36:30 +02:00
Charles Papon 3b66d986a8 Fix cpu sending instruction memory request while being halted by the DebugPlugin 2017-07-29 18:20:22 +02:00
Charles Papon 43253f61c1 Update Murax info 2017-07-29 02:52:57 +02:00
Charles Papon fa887d3830 Add pipelining option (hit 60 Mhz) 2017-07-29 02:52:03 +02:00
Charles Papon 3bdf020c67 Add interrupts and timer to Murax 
8KB ram is the default now
 2017-07-29 01:59:17 +02:00
Charles Papon 823ac353ff Add Murax SoC (very light, work on ice40) 2017-07-28 21:25:49 +02:00
Dolu1990 1450077b70 Add Murax SoC (wip) 2017-07-28 14:16:30 +02:00
Charles Papon 493f7721cb All FreeRTOS tests are now passing 2017-07-28 00:07:51 +02:00
Charles Papon 800e9e79a5 freertos regression now include O0 and O3 for rv32i and rv32im 2017-07-27 01:23:50 +02:00
Charles Papon 6b3e2dbe7d Add FreeRTOS test regression (FREERTOS=yes) 
Multithreaded regression
 2017-07-26 23:38:59 +02:00
Charles Papon 10d282b2ef Add DBusSimple early injection feature (better DMIPS) 2017-07-26 23:36:25 +02:00
Charles Papon 6d117f5c81 Fix DataCache bug (interaction between the victim buffer and the memory read request in execute/memory stages) 
freeRTOS pass
 2017-07-23 22:58:26 +02:00
Charles Papon 9fe4e1d54d Package refractoring VexRiscv -> vexriscv Plugin -> plugin 2017-07-23 13:28:17 +02:00
Charles Papon 4b5bf7d807 Briey Area down by 10% by spliting the memory system in two (System, Debug) 2017-07-23 01:11:33 +02:00
Charles Papon 37c338ec98 Avalon add read response support. 
Fix debug instruction injection and IBusSimplePlugin interraction
 2017-07-21 20:39:54 +02:00
Charles Papon 54f785b1a3 Add full avalon support (pass regression) 2017-07-21 17:40:45 +02:00
Charles Papon 52f5020e64 Rename some regression commands 
Add Avalon regressions (PASS)
DebugModule read response is now 1 cycle latency
 2017-07-21 14:32:49 +02:00
Charles Papon 575a410786 Avalon regression (WIP) 2017-07-20 14:20:19 +02:00
Charles Papon 570f0e1e3e D$ remove the coupling between the mem.cmd.ready >> victim logic >> cpu halt by using halfPipe => Better practical FMax 2017-07-20 14:20:19 +02:00
Dolu1990 950944e040 typo fix 2017-07-19 18:36:30 +02:00
Dolu1990 8643086fc0 Add Briey area and timings into readme 2017-07-19 18:34:16 +02:00
Dolu1990 02c9b0be75 readme add full no cache 2017-07-17 16:52:36 +02:00
Charles Papon 42e546ecd9 Add fullNoMmuNoCache config 2017-07-17 16:45:06 +02:00