230 commits

Author	SHA1	Message	Date
Dolu1990	36438bd306	iterative mul improvments	2018-03-09 20:00:50 +01:00
Dolu1990	674ab2c594	experimental iterative mul/div combo	2018-03-09 19:07:26 +01:00
Dolu1990	5228a53293	MuraxSim improve simulation Speed	2018-03-06 12:20:39 +01:00
Dolu1990	9b2cd7b234	MuraxSim add switch	2018-03-06 12:17:15 +01:00
Dolu1990	53970dd284	SpinalHDL 1.1.4 ... Now the CsrPlugin is waiting that the memory/writeback stages are empty before reading/writing things	2018-03-05 14:34:59 +01:00
Dolu1990	ccad64def5	Pipeline CSR isWrite	2018-02-26 10:19:33 +01:00
Dolu1990	2b6185b063	Decoding logic : Add primes duplication removal	2018-02-25 08:57:31 +01:00
Dolu1990	2b6f43cef8	Fix Murax memory mapping range	2018-02-25 08:57:31 +01:00
Dolu1990	5260ad5c35	Decoding lib cleaning	2018-02-25 08:57:31 +01:00
Dolu1990	137b1ee32c	Briey testbench, fix io_coreInterrupt to zero to avoid external interrupt set by random boots values	2018-02-22 22:36:13 +01:00
Dolu1990	d957934949	Fix ICache exception priority over miss reload	2018-02-19 22:44:46 +01:00
Dolu1990	d0e963559a	Update readme with the new ICache implementation	2018-02-18 23:48:11 +01:00
Dolu1990	93110d3b95	Add jump priority managment in PcPlugins	2018-02-16 14:27:20 +01:00
Dolu1990	506e0e3f60	New faster/smaller/multi way instruction cache design. ... Single or dual stage	2018-02-16 02:21:08 +01:00
Dolu1990	3853e0313b	SynthesisBench cleaning/experiments	2018-02-11 14:53:42 +01:00
Dolu1990	0e6ae682b1	Add architecture section describing plugins in the readme	2018-02-09 00:44:27 +01:00
Dolu1990	57ebfee2e6	Add more axi bridges	2018-02-08 21:39:22 +01:00
Dolu1990	3ee111e100	Update readme (gcc stuff)	2018-02-05 16:34:10 +01:00
Dolu1990	d4b05ea365	Remap Briey/Murax onChipRam to 0x80000000 to avoid having memory at the null pointer location ... Commit missing file Update dhrystone hex to use GP. 1.44 DMIPS/Mhz	2018-02-05 16:16:27 +01:00
Dolu1990	4729e46763	Add DummyFencePlugin	2018-02-03 12:28:53 +01:00
Dolu1990	f13dba847c	Add custom csr gpio example	2018-02-02 11:14:55 +01:00
Dolu1990	b7d8ed8a81	Add onWrite/onRead/isWriting/isReading on the CsrPlugin	2018-02-01 21:28:28 +01:00
Dolu1990	4ee2482cbf	Fix custom_csr regression against random ibus stall	2018-01-31 18:33:21 +01:00
Dolu1990	d2e5755df4	revert removed code by mistake	2018-01-31 18:29:30 +01:00
Dolu1990	30b05eaf96	Add CsrInterface to allow custom CSR addition ... Add CustomCsrDemoPlugin as a show case	2018-01-31 18:13:42 +01:00
Dolu1990	bdbf6ecf17	BranchPrediction DYNAMIC_TARGET add source PC tag to only consume entries on branch instructions	2018-01-29 14:52:31 +01:00
Dolu1990	0d318ab6b9	Add DYNAMIC_TARGET branch prediction (1.41 DMIPS/Mhz) ... Add longer timeouts in the regressions tests	2018-01-29 13:17:11 +01:00
Dolu1990	307c0b6bfa	Now mret and ebreak are only allowed in CSR machine mode	2018-01-28 16:34:55 +01:00
Dolu1990	93da5d29bc	Fix dhrystone referance log	2018-01-28 16:34:55 +01:00
Dolu1990	26732942e5	Update DMIPS/Mhz ... Add cached config with maximal performance settings FullBarrielShifterPlugin can now be configured to do everything in the execute stage	2018-01-25 01:11:57 +01:00
Dolu1990	3b3bbd48b9	SpinalHDL 1.1.3 => Now Verilog rom are emited into separated bin files	2018-01-20 18:29:33 +01:00
Dolu1990	6a521a8d13	Better MuraxSim gui ... Add MuraxSim in the readme	2018-01-09 08:59:17 +01:00
Dolu1990	9a89573942	SpinalHDL 1.1.2 ... Add Murax setup with Mul Div Barriel	2018-01-06 22:09:42 +01:00
Dolu1990	43d3ffd685	CsrPlugin : Now wait that the whole pipeline (including writeback) is empty before executing interruptions. This make the separation between context switching clear and avoid on atomic instructions failure	2018-01-04 17:37:23 +01:00
Dolu1990	2b7465e5df	Add more atomic tests (PASS)	2018-01-04 16:16:22 +01:00
Dolu1990	611f2f487f	Fix DataCache atomic integration into DBusCachedPlugin ... Atomic is passing basic tests	2018-01-04 15:24:00 +01:00
Dolu1990	4637e6cb48	Fix DecodingSimplePlugin model building when reinvocation is done one a preexisting opcode. ... add Atomic test flow	2018-01-04 14:43:30 +01:00
Dolu1990	468dd3841e	Add Atomic LR SC support to the DBusCachedPlugin via reservation entries buffer	2018-01-04 13:16:40 +01:00
Dolu1990	4ed19f2cc5	SpinalHDL 1.1.1	2017-12-30 03:36:57 +01:00
Dolu1990	0d39e38906	SpinalHDL 1.1.0	2017-12-28 13:49:39 +01:00
Dolu1990	3c0588eb4b	remove MuraxSim fixed path	2017-12-19 22:33:46 +01:00
Dolu1990	7f2b2181c1	SpinalHDL 1.0.3	2017-12-19 21:21:16 +01:00
Dolu1990	37849b7a66	Spinal 1.0.2 sim update	2017-12-19 00:40:52 +01:00
Dolu1990	ebda7526b5	MuraxSim 1.0.0	2017-12-17 17:57:09 +01:00
Dolu1990	dda5372a6c	Fix typo	2017-12-14 01:05:06 +01:00
Dolu1990	d6e0761065	Fix led gui refresh rate	2017-12-14 01:04:31 +01:00
Dolu1990	2259c9cb0f	Add SpinalHDL sim (1.0.0)	2017-12-14 00:57:12 +01:00
Dolu1990	e1b86ea511	SpinalHDL 0.11.4 update	2017-12-01 11:19:23 +01:00
Dolu1990	586d3ed286	Update formal VexRiscv to halt on missaligned dbus	2017-11-26 15:30:48 +01:00
Dolu1990	4de0aac469	Merge branch 'formal'	2017-11-24 14:03:25 +01:00