Dolu1990
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98eaeaabc8
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fix regression.mk typo
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2021-01-30 22:34:54 -01:00 |
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Dolu1990
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6aa6191240
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Merge branch 'master' into dev
# Conflicts:
# build.sbt
# src/main/scala/vexriscv/Riscv.scala
# src/main/scala/vexriscv/ip/DataCache.scala
# src/main/scala/vexriscv/plugin/DBusSimplePlugin.scala
# src/main/scala/vexriscv/plugin/MmuPlugin.scala
# src/test/cpp/regression/makefile
# src/test/scala/vexriscv/TestIndividualFeatures.scala
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2021-01-30 20:30:21 +01:00 |
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Dolu1990
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2e8a059c77
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Fix travis verilator
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2020-06-07 11:33:24 +02:00 |
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Dolu1990
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23b8c40cab
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update travis verilator
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2020-04-28 16:19:00 +02:00 |
japm48
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6547eefffd
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Murax on arty_a7: fix mkdir error
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2020-02-11 18:58:43 +01:00 |
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japm48
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163611bd11
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Murax on arty_a7: fix RAMB type on soc_mmi.tcl
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2020-02-11 18:49:56 +01:00 |
sebastien-riou
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2bcddd333d
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forced the commit of missing TCL files
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2020-01-17 00:33:02 +01:00 |
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sebastien-riou
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97b2838d18
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Murax on Digilent Arty A7-35
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2020-01-16 21:58:55 +01:00 |
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sebastien-riou
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de9f704de2
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better pin names in scala, bootloader without magic word
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2020-01-13 21:58:08 +01:00 |
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sebastien-riou
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bfb0b54f9b
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readme for XIP on Murax improved
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2020-01-12 19:52:27 +01:00 |
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sebastien-riou
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b866dcb07f
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XIP on Murax improvements
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2020-01-12 16:08:14 +01:00 |
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Charles Papon
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633e057d11
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Split machine os regression in two smaller parts
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2019-04-21 20:30:58 +02:00 |
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Dolu1990
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d18dcc0540
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Update regression.mk
reduce linux regression time a bit
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2019-04-21 13:49:05 +02:00 |
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Dolu1990
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fc4c078f17
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Update regression.mk
Reduce machine os time
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2019-04-21 13:36:25 +02:00 |
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Charles Papon
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7e91b5e446
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Fix travis
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2019-04-21 12:55:01 +02:00 |
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Charles Papon
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963805ad48
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Bring freertos back in tests
Better travis test range
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2019-04-21 12:50:28 +02:00 |
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Charles Papon
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3b0f2e9551
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better travis timings
travis job naming
reduce verilator cache size
Fix dcache test timeout
travis cleaning
travis wip
verilator wip
fix java 10 compilation
Travis wip
travis rework
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2019-04-20 14:56:56 +02:00 |
Tim Ansell
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7594cbd902
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Fixing images in README in iCE40-hx8k_breakout_board_xip directory too.
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2019-02-22 14:57:07 -08:00 |
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Tim Ansell
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5c6cc29304
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Fixing other image.
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2019-02-22 14:55:18 -08:00 |
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Tim Ansell
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c9f4a09de0
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Fix image in README.
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2019-02-22 14:52:09 -08:00 |
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Dolu1990
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dcdfa79024
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fix run-main into runMain
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2019-01-03 20:07:38 +01:00 |
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Dolu1990
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a2d3cfbfc1
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Remove unused file
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2018-09-27 00:56:20 +02:00 |
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Dolu1990
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6dde73f97c
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Murax demo with XIP is now fully defined in SpinalHDL
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2018-09-27 00:55:30 +02:00 |
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Dolu1990
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1e3b75ef1d
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xip typo
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2018-09-23 22:06:21 +02:00 |
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Dolu1990
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ff1d1072a7
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XIP is physicaly working on murax
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2018-09-19 00:09:14 +02:00 |
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Dolu1990
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b51ac03a5e
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murax xip flash integration wip
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2018-09-18 16:53:26 +02:00 |
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Tim 'mithro' Ansell
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1c5ee779ef
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Generate Murax with the flashy program.
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2018-07-20 19:04:59 -07:00 |
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Tim 'mithro' Ansell
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acbce9fb57
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Adding a README file with images.
Should make it much easier to get started.
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2018-07-20 19:04:41 -07:00 |
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Tim 'mithro' Ansell
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051d0c27d4
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Rename example makefiles to more normal `Makefile`.
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2018-07-20 18:31:13 -07:00 |
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Tim 'mithro' Ansell
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5465c0d4c0
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Adding sudo-prog to hx8k_breakout_board example.
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2018-07-20 18:30:26 -07:00 |
Dolu1990
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b3564e1b7e
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Fix Murax script flow (without rom file)
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2018-01-21 15:39:10 +01:00 |
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Dolu1990
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3b3bbd48b9
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SpinalHDL 1.1.3 => Now Verilog rom are emited into separated bin files
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2018-01-20 18:29:33 +01:00 |
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Dolu1990
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c3d950fb13
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Clean script folder
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2017-12-29 13:18:14 +01:00 |
Jakob Bornecrantz
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617a2948d0
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Port to iCE40HX8K-EVB
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2017-12-27 21:21:55 +00:00 |
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Charles Papon
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c033b32fc9
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scripts/murax remove jtag pullup which apparently break the functionality
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2017-08-03 23:59:48 +02:00 |
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Charles Papon
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d962406b26
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scripts/murax better makefile, add pullup on jtag interface
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2017-08-03 23:22:57 +02:00 |
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Charles Papon
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568c7d1365
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Update murax readme
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2017-07-31 13:57:34 +02:00 |
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Charles Papon
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c16a53c388
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Refractoring of some arbitration signals
Add UART into Murax
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2017-07-31 13:34:25 +02:00 |
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Charles Papon
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087e3dda89
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Add Murax scripts
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2017-07-29 22:43:43 +02:00 |