53300c4116
Add area and FMax in readme
...
Add Synthesis bench
2017-07-16 13:50:19 +02:00
37ea699c55
Add Synthesis bench
2017-07-16 03:29:50 +02:00
6930e76042
Remove mepc from smallest CSR config
...
Better readme
2017-07-16 00:44:23 +02:00
bc792a8655
Fix UartRx sim
2017-07-15 19:05:34 +02:00
74becb6633
Add VexRiscvAvalon QSysify
2017-07-15 09:41:39 +02:00
12d21a08e8
Add DebugPlugin avalon
2017-07-14 19:28:22 +02:00
d3dcfcec06
Add toAvalon bridge to cached bus
...
Add VexRiscvAvalon demo
2017-07-14 18:04:41 +02:00
b9cbb27b81
Add Briey informations
2017-07-09 18:02:01 +02:00
f51f28164a
Fix info to flush data cache
...
Briey sim add VGA GUI (SDL2)
Add DE0-Nano Briey support
2017-07-09 01:00:46 +02:00
8d34c04425
Fix CsrPlugin case issue
...
Better DBusSimplePlugin FMax with catch enables
SrcPlugin can now insert SRC1 and SRC2 in the execute mode for lower area usage and combinatorial path balancing
2017-06-27 19:37:46 +02:00
e9ab3d71d5
update readme
...
add uart.elf binary for testing
2017-06-26 14:44:52 +02:00
4d7455f9c3
add retiming to the dataCache waysHit
...
Add exception catches in the default briey configuration
2017-06-26 14:02:25 +02:00
e9e7cf9e7a
Add briey tracing
...
Better debugPlugin implementation
Fix SimpleDBus/IBus into AXI bridge (cmd transaction removing)
Add SingleInstructionLimiterPlugin for debug purposes
2017-06-24 14:09:12 +02:00
edf1b4ed5a
Cleaning, better jtag perf
2017-06-18 16:10:27 +02:00
a94343b98a
Update to SpinalHDL 0.10.14
2017-06-17 15:15:19 +02:00
c85f6b89de
Update verilator requirements
2017-06-15 20:27:20 +02:00
03be1f354f
Better readme
2017-06-15 14:06:32 +02:00
bc90331c49
Cleaning
2017-06-15 13:54:34 +02:00
88a2c4a603
Cleaning/Add documentation
2017-06-15 13:44:21 +02:00
835dd4ad50
Add CSR
2017-06-15 11:16:11 +02:00
f8678698fc
Briey improve AXI FMax
...
Faster debugginPlugin regression
2017-06-11 11:52:59 +02:00
cbc770deb3
Improve TCP sockets latency
2017-06-10 19:38:42 +02:00
9b9d9e2582
Add Uart monitor in the briey testbench
2017-06-10 16:09:14 +02:00
11a63491bd
Add YAML feature to store CPU info
2017-06-09 16:06:18 +02:00
4b9668c063
Remove speed factor overriding when Trace
2017-06-09 08:41:12 +02:00
f46ec583d6
Briey is now working with DataCache on FPGA
2017-06-07 23:02:34 +02:00
8dcf5cf68a
Add missing import in Briey testbench
2017-06-07 16:56:29 +02:00
8da413dec3
Briey SoC is now working with openOCD TCP JTAG connection. (GDB OK)
...
Add SDRAM Verilator model
2017-06-07 04:19:35 +02:00
1e18daecc0
Add ICache and DCache axi bridges functions
...
Add StaticMemoryTranslationPlugin
2017-06-01 17:54:56 +02:00
ac16558b6b
Add haltItByOther
...
Axi4, remove some pipelining
2017-05-30 17:49:29 +02:00
6b62d8da52
VexRiscv in Briey SoC is working on FPGA (including jtag debugging)
2017-05-29 21:17:14 +02:00
213e154b40
Fix regression test debugPlugin bus
2017-05-28 17:41:09 +02:00
8dddc7e334
GDB + openOCD successfully connect !
2017-05-25 13:36:54 +02:00
75f6b78daf
OpenOCD successfuly connected to target
2017-05-24 23:53:31 +02:00
1efed60307
Fix DebugPlugin
...
Add DebugPlugin regression (PASS)
2017-05-22 19:23:11 +02:00
cc875d1c0b
Add TCP server socket to manage debug access from openOCD (as instance)
2017-05-22 00:42:19 +02:00
5cda2632df
Start implementing debugPlugin test infrastructures
2017-05-21 23:50:40 +02:00
9995c5109d
move tests
2017-05-21 16:53:48 +02:00
6c1d953647
DebugPlugin fully implemented
2017-05-20 18:15:15 +02:00
619739d33a
preliminary DebugPlugin
2017-05-20 15:16:45 +02:00
cabf602efc
Update README.md
2017-05-19 17:13:33 +02:00
a5364ad001
Add flush support instruction into the instruction cache
2017-05-19 11:20:33 +02:00
736478ff1d
CsrPlugin now catch illegal CSR access (wrong address + to low privilege level)
2017-05-09 00:40:44 +02:00
fe184636dd
Improve CsrPlugin FMax
2017-05-08 22:59:05 +02:00
c69fdf7987
Add basics of the USER mode to CsrPlugin
2017-05-07 23:41:54 +02:00
579e93bb5a
Rename MachineCsr plugin into CsrPlugin
2017-05-07 22:26:17 +02:00
392f3a7d8c
Add PrivilegeService (User) (not implemented)
...
Split caches from their plugins file
2017-05-07 20:16:41 +02:00
a51c27970b
Add opcode for clean/invalidate the datacache
...
Change mmu opcodes
2017-05-07 16:02:55 +02:00
4d6a6fbb02
Fix Instruction Data cache exceptions
...
Pass all tests including CSR/FreeRTOS
2017-05-07 12:51:47 +02:00
ca1bc9cf69
DataCache plugin now support all exceptions
2017-05-07 10:44:41 +02:00
Dolu1990