Dolu1990
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3739b9ac88
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plic update
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2023-08-29 08:58:48 +02:00 |
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Charles Papon
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fd0f23abb6
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Merge branch master into dev
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2023-07-11 04:19:06 +08:00 |
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Dolu1990
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ba6dcb1789
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Add a few privSpec tests
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2023-04-27 14:56:41 +02:00 |
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Dolu1990
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cb0bacfce9
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implement dummy pmp as 1.10 spec says
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2023-03-31 10:12:52 +02:00 |
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Dolu1990
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b4d5a315cf
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CsrPlugin implement dummy pmp if no pmp is there
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2023-03-31 10:11:53 +02:00 |
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Dolu1990
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8195bec788
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privSpec now check FPU dirty flag
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2023-03-23 11:24:38 +01:00 |
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Dolu1990
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b01490b5f3
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Implement counteren (1.10+ spec)
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2023-03-23 08:53:10 +01:00 |
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Dolu1990
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0e59a56bd1
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add privSpec test
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2023-03-22 16:25:23 +01:00 |
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Dolu1990
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bba022b746
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fix a few csr related WARL (minor)
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2023-03-22 16:25:03 +01:00 |
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Dolu1990
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4972a27ae9
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More verbose main.cpp on failure, fix C.ADDSP regfile initialisation
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2023-03-22 11:06:23 +01:00 |
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Charles Papon
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25eda80fee
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FpuTest document how to install berkley testfloat
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2023-03-10 14:46:21 +08:00 |
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Dolu1990
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6f76a45e7d
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update mmu test
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2023-02-23 15:54:39 +01:00 |
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Dolu1990
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a40d5f19b2
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Fix MMU A and D flag handeling
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2023-02-23 12:00:08 +01:00 |
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Dolu1990
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344b2d4eda
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TestIndividual supervisor missing CSR=yes
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2023-02-23 11:59:13 +01:00 |
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Dolu1990
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773f268f37
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Fix FPU test syntax
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2022-12-01 12:04:16 +01:00 |
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Dolu1990
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eafeb5fe49
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Add EmbeddedRiscvJtag.debugCd
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2022-11-28 11:04:02 +01:00 |
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Dolu1990
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0bfaf06a4a
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main.cpp add VEXRISCV_JTAG=yes
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2022-11-10 13:43:14 +01:00 |
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Dolu1990
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d70794f252
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fix regression
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2022-10-27 15:38:34 +02:00 |
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Dolu1990
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5d0deb20b3
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Fix regression compilation
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2022-10-27 15:20:55 +02:00 |
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Dolu1990
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4cd3f65296
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Add official RISC-V debug support (WIP, but can already load / step / run code via openocd telnet)
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2022-10-19 12:36:45 +02:00 |
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Dolu1990
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959e48a353
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Fpu now set csr status fs on FPU csr write
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2022-10-06 11:13:57 +02:00 |
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Dolu1990
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3b8270b82b
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#241 Fix Murax/Briey TB timeouts
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2022-04-11 11:59:41 +02:00 |
Andreas Wallner
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2d2017465e
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Fix reset vector of GenCustomSimdAdd
With the old reset vector half of the tests fail since
they expect the CPU to start at 0x80000000.
(e.g. I-IO, I-NOP, I-LUI, etc.)
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2022-04-03 02:55:42 +02:00 |
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Dolu1990
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e558b79582
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Fix Briey simulation floating rxd blocking the uart #238
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2022-02-22 16:15:14 +01:00 |
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Dolu1990
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5714680278
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Merge branch 'master' into dev
# Conflicts:
# build.sbt
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2022-02-05 11:32:40 +01:00 |
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Dolu1990
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8b2f107d46
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verilator++
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2022-02-04 15:10:57 +01:00 |
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Dolu1990
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b8e904e43f
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syncronize golden model with dut for lrsc reservation
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2022-01-10 19:55:28 +01:00 |
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Dolu1990
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6e77f32087
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sim golden model lrsc reservation sync
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2022-01-10 16:08:38 +01:00 |
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Dolu1990
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da53de360f
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Fix lrsc from last commit
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2022-01-10 14:21:20 +01:00 |
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Dolu1990
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dd12047aa7
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Merge branch dev (SpinalHDL 1.6.1)
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2021-12-15 09:22:46 +01:00 |
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Dolu1990
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acf14385d8
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#213 disable pmp test with region overlapping
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2021-10-22 17:24:51 +02:00 |
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Dolu1990
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b807254759
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Briey and Murax verilators now use FST instead of VCD
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2021-09-22 12:57:27 +02:00 |
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Dolu1990
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68e704f309
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restore avalon d$ tests
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2021-09-02 15:42:33 +02:00 |
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Dolu1990
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5f2fcc7d0f
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Merge branch 'dev'
(SpinalHDL 1.6.0)
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2021-07-20 10:39:09 +02:00 |
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Dolu1990
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df7ac05db9
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Update 2.13 compatibility
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2021-06-23 11:48:38 +02:00 |
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Dolu1990
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d67fe72de9
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Merge branch 'dev'
# Conflicts:
# build.sbt
# src/test/cpp/regression/main.cpp
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2021-06-15 15:54:13 +02:00 |
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Dolu1990
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1497001ebd
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Update FpuTest with the new rs1/rs2 store mapping
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2021-06-09 13:37:31 +02:00 |
Samuel Lindemer
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d49f8d1b58
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Merge branch 'dev' into new_pmp
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2021-05-28 13:56:15 +02:00 |
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Samuel Lindemer
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24a534acff
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All tests passing on new PMP plugin
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2021-05-28 13:54:55 +02:00 |
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Samuel Lindemer
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4a2dc0ff5f
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Fix granularity control
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2021-05-27 15:50:45 +02:00 |
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Samuel Lindemer
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61f68f0729
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Refactor for new CSR API (PMP reads still broken)
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2021-05-26 15:29:27 +02:00 |
Alexis Marquet
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8122cc9b5e
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fixed priority of == & != as seemed logical to get less warnings when building
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2021-05-17 18:51:33 +02:00 |
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Dolu1990
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fa2899a1a2
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Merge branch 'debugPlugin' into dev
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2021-04-26 11:11:38 +02:00 |
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Dolu1990
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45e67ccf56
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sync
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2021-04-26 11:10:55 +02:00 |
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Dolu1990
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32e4ea406f
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update #176 when DebugPlugin ebreak are enabled it disable CsrPlugin ebreak. Also, DebugPlugin ebreak can be disabled via the debug bus.
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2021-04-22 13:59:33 +02:00 |
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Dolu1990
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bfe65da1eb
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implement #176 DebugPlugin.allowEBreak is now disabled until the debug bus is used.
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2021-04-20 23:23:18 +02:00 |
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Samuel Lindemer
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15137742fc
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Merge branch 'dev' into new_pmp
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2021-04-12 13:23:10 +02:00 |
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Samuel Lindemer
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b41db0af93
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Prevent PMP access from U-mode, fix tests
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2021-04-12 13:20:15 +02:00 |
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Samuel Lindemer
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bf399cc927
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Initial commit of optimized PMP plugin
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2021-04-12 13:20:15 +02:00 |
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Dolu1990
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3a34b8dae2
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Merge branch 'dev' into fiber
# Conflicts:
# src/main/scala/vexriscv/demo/smp/VexRiscvSmpCluster.scala
# src/main/scala/vexriscv/plugin/MulPlugin.scala
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2021-03-15 10:35:02 +01:00 |