Charles Papon
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179e7f7b4c
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IBusCachedPlugin add asyncTagMemory option
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2017-04-05 14:25:11 +02:00 |
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Charles Papon
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2b24cbc8e1
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Add pessimistic harzard options
Add separated add/sum option in srcPlugin
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2017-04-04 00:25:39 +02:00 |
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Charles Papon
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acb85a1fb8
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Add some decoder comments
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2017-04-03 01:33:54 +02:00 |
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Charles Papon
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8ff05bd2a8
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Much better decoder using Quine-Mc Cluskey
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2017-04-02 21:05:25 +02:00 |
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Charles Papon
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a9f7177181
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Data cache pass dhrystone benchmark.
Data cache todo -> bus error handling
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2017-04-01 17:06:59 +02:00 |
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Charles Papon
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2f384364d8
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Data cache WIP
refractoring
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2017-03-31 15:20:51 +02:00 |
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Charles Papon
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26597f78cd
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cleaning
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2017-03-31 11:06:40 +02:00 |
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Charles Papon
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19fe998a52
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Instruction cache is now able to catch bus errors
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2017-03-30 17:34:24 +02:00 |
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Charles Papon
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95585b4d9a
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Add instruction cache plugin (tested)
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2017-03-30 10:03:53 +02:00 |
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Charles Papon
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32d32845bd
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Add tests for iRsp, dRsp access faults
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2017-03-28 20:25:58 +02:00 |
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Charles Papon
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2cb0e90077
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refractoring/cleaning
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2017-03-28 01:53:37 +02:00 |
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Charles Papon
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62a55c4cf4
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Add IRsp/dRsp ready + error capabilities to stall the bus and to generate access error exceptions
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2017-03-28 01:24:29 +02:00 |
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Charles Papon
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eecc1e6b18
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Add MachineCsr.mbadaddr logics
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2017-03-27 18:35:27 +02:00 |
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Charles Papon
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349d600182
|
Better readme
cleaning
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2017-03-27 00:33:34 +02:00 |
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Charles Papon
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e5148e5e05
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Better readme
|
2017-03-26 22:43:00 +02:00 |
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Charles Papon
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70e8bc503e
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Add readme
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2017-03-26 22:38:07 +02:00 |
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Charles Papon
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91c52f4e46
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Decoder now catch illegal instructions
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2017-03-26 18:02:48 +02:00 |
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Charles Papon
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c5520656e5
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Now able to catch missaligned instruction/data addresses
Modify arbitration with an flushAll + isFlushed
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2017-03-26 17:20:07 +02:00 |
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Charles Papon
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4000191966
|
FreeRTOS tested
removeIt no more colapse bubbles
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2017-03-25 16:44:42 +01:00 |
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Charles Papon
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9bbf3ee3e7
|
MachineCsr fix csr set/clear with zero
MachineCsr pass external/timer interrupts test
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2017-03-24 17:40:37 +01:00 |
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Charles Papon
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72d65841d2
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MachineCsr pass simple interrupt and exception tests
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2017-03-23 23:12:44 +01:00 |
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Charles Papon
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ed0660237f
|
MachineCsr wireing/logic done
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2017-03-23 01:00:24 +01:00 |
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Charles Papon
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de4c2470c8
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MachineCsr add mcycle and minstret
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2017-03-22 20:38:43 +01:00 |
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Charles Papon
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94770f8e0b
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Add MachineCsr (untested)
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2017-03-22 18:29:34 +01:00 |
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Charles Papon
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e9d3977737
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Add Arbitration.flushIt
Add ExceptionService
Add unremovableStage
Add MachineCsr (untested)
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2017-03-21 18:40:50 +01:00 |
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Charles Papon
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c49373f3d1
|
Fix missing JAL, JALR encoding
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2017-03-21 10:29:09 +01:00 |
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Charles Papon
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787682d4f6
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Add comments
Some refractoring
|
2017-03-20 14:49:49 +01:00 |
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Charles Papon
|
51058f851e
|
Renaming
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2017-03-20 12:37:53 +01:00 |
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Charles Papon
|
ecf853f491
|
Add Static/Dynamic branch prediction
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2017-03-20 12:37:20 +01:00 |
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Charles Papon
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d569242124
|
Add Static branch prediction in decode stage
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2017-03-19 23:27:35 +01:00 |
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Charles Papon
|
88dee6d2bc
|
Reduce area with reg[0] optimisation
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2017-03-18 19:32:54 +01:00 |
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Charles Papon
|
fc1bb7249a
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Add trace option to regresion
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2017-03-18 14:06:42 +01:00 |
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Charles Papon
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5e9da0f27a
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Add self checked dhrystone test
|
2017-03-18 12:32:14 +01:00 |
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Charles Papon
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31db6511dc
|
Fix performance of removed instruction which halt were halting the pipeline
|
2017-03-18 10:51:55 +01:00 |
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Charles Papon
|
20ca348707
|
Fix dCmd sent while the execute stage is removed
Pass dhrystone benchmark without error !
|
2017-03-17 21:26:42 +01:00 |
|
Charles Papon
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7517ac797d
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Add MUL/DIV/REM support with plugins (pass Riscv-Tests)
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2017-03-17 11:45:01 +01:00 |
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Charles Papon
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52a524be06
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Add light shifter plugin
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2017-03-16 15:11:06 +01:00 |
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Charles Papon
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401be6ca83
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Reorganize project
|
2017-03-16 13:14:25 +01:00 |
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Charles Papon
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bf5bebda08
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PcManager now drive PC asyncronously (use 1 cycle less in jump)
Fix bypass logic when read/write r0
Disable REGFILE_WRITE_VALID in decod stage when r0 is written
|
2017-03-15 21:10:44 +01:00 |
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Charles Papon
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83232e9860
|
Faster pipeline arbitration logic (200 Mhz on cyclone IV c6)
Branch plugin with jump in execute or memory stages (parameter)
|
2017-03-15 20:02:56 +01:00 |
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Charles Papon
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c6610ea454
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Fix halt arbitrations
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2017-03-15 17:14:58 +01:00 |
|
Charles Papon
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11797fbb6e
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Add sim performance print
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2017-03-14 23:25:04 +01:00 |
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Charles Papon
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70d910e7d7
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Load/Store pass Riscv-Tests
|
2017-03-14 23:00:24 +01:00 |
|
Charles Papon
|
7065ed5d93
|
All base instruction pass Riscv-Test (load/store not tested)
|
2017-03-14 20:13:35 +01:00 |
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Charles Papon
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ad6964f0bb
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Classify tests
Riscv-test integration wip
|
2017-03-14 00:42:48 +01:00 |
|
Charles Papon
|
df99a0d963
|
Better decoding
|
2017-03-13 18:30:37 +01:00 |
|
Charles Papon
|
e36c90af03
|
Add decoder bench
|
2017-03-13 16:17:57 +01:00 |
|
Charles Papon
|
9fc82c9736
|
Pass verilator simple literal, add, jump
|
2017-03-12 20:12:40 +01:00 |
|
Dolu1990
|
ec4837a744
|
wip
|
2017-03-12 12:39:33 +01:00 |
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Dolu1990
|
cb1b73bc2b
|
Add branch
|
2017-03-11 19:07:08 +01:00 |