Commit Graph

734 Commits

Author SHA1 Message Date
Charles Papon f249bbc60a Merge remote-tracking branch 'origin/tmp' 2019-05-18 20:35:28 +02:00
Charles Papon b40dc06b29 SpinalHDL 1.3.5 2019-05-18 19:56:03 +02:00
Dolu1990 abb7bd99ab
Merge pull request #75 from SpinalHDL/dev
Merge dev (SpinalHDL 1.3.4)
2019-05-10 17:28:09 +02:00
Charles Papon 8201cff7ff SpinalHDL 1.3.4 2019-05-10 14:27:14 +02:00
Charles Papon db307075cf Merge branch 'AHB' into dev
# Conflicts:
#	src/main/scala/vexriscv/plugin/DBusSimplePlugin.scala
#	src/main/scala/vexriscv/plugin/IBusSimplePlugin.scala
2019-05-07 17:21:52 +02:00
Charles Papon 01db217ab9 Add supervisor support in the ExternalInterruptArrayPlugin 2019-05-06 16:23:43 +02:00
Dolu1990 3094f8b349 Merge remote-tracking branch 'origin/dBusCachedRelaxMmuTranslation' 2019-05-06 01:36:56 +02:00
Dolu1990 91f6bf5139 Merge branch 'dBusCachedRelaxMmuTranslation'
# Conflicts:
#	src/test/scala/vexriscv/TestIndividualFeatures.scala
2019-05-06 01:36:11 +02:00
Charles Papon d27fa4766d DBusCachedPlugin add earlyWaysHits in regressions 2019-05-06 00:05:40 +02:00
Charles Papon d12decde80 Remove test which had issues with the testbench ref checks because of getting passed delayed 2019-05-05 22:46:46 +02:00
Charles Papon 8f1b980337 Revert "Add DBusCachedPlugin.relaxedMemoryTranslationRegister option"
This reverts commit 5f18705358.
2019-05-05 22:29:33 +02:00
Charles Papon 5f18705358 Add DBusCachedPlugin.relaxedMemoryTranslationRegister option 2019-05-05 21:19:48 +02:00
Charles Papon c738246610 Remove the legacy pipelining from Axi4 cacheless bridges 2019-05-01 12:03:01 +02:00
Charles Papon 7d99a70e9c Switch to released SpinalHDL 2019-05-01 12:02:27 +02:00
Charles Papon 02db756b21 Merge remote-tracking branch 'origin/master' into dev 2019-04-29 16:56:04 +02:00
Dolu1990 fa13e46e87
Merge pull request #71 from xobs/mmu-2-stage
Mmu 2 stage
2019-04-26 14:25:29 +02:00
Sean Cross d1e215e312 caches: work without writeBack stage
In the case of an MMU miss, the data caches will create a retry branch port.
These currently implicitly go into the memory/writeBack stage, however
not all CPUs have this stage.

Place the retry branch port into the correct stage.

Signed-off-by: Sean Cross <sean@xobs.io>
2019-04-26 18:02:43 +08:00
Sean Cross b2f387ccac MmuPlugin: fix generation without writeBack stage
If there is no writeBack stage, the elaboration step would hit a
NullPointerException when trying to insert into the writeBack stage.

Instead, pull from the most recent stage, which is where MMU access
should reside.

Signed-off-by: Sean Cross <sean@xobs.io>
2019-04-26 18:01:35 +08:00
Dolu1990 6fc5406901 Merge branch 'linux' 2019-04-25 23:20:01 +02:00
Dolu1990 0edc781b36 Add some coremark results 2019-04-25 23:18:45 +02:00
Charles Papon 10255f2f81 Update readme 2019-04-25 21:11:23 +02:00
Charles Papon d64589cc48 Add configs without memory/writeback stages in regressions
Add rfReadInExecute configs in regressions
Fix ShiftPluginLight and DBusSimplePlugin for configs with rfReadInExecute stage configs
2019-04-25 17:36:13 +02:00
Charles Papon 431bec84fb Switch to SpinalHDL 1.3.3 (release) 2019-04-24 22:17:46 +02:00
Charles Papon 017e17f9fa Update synthesis results in the readme 2019-04-24 12:32:57 +02:00
Charles Papon 74e5cc49f9 Add the linux config into the synthesis bench 2019-04-24 12:32:37 +02:00
Charles Papon a331f35724 Icestorm flow now use nextpnr 2019-04-24 12:32:24 +02:00
Charles Papon b654d824ad remove DebugPlugin from linux.scala, and set static branch prediction 2019-04-23 21:55:54 +02:00
Charles Papon 266bdccc2e update Riscv software model lrsc implementation 2019-04-23 21:55:54 +02:00
Charles Papon 4078f84e8f Dhrystone regression now also run coremark 2019-04-23 21:55:54 +02:00
Charles Papon c6dbaa52f6 Longer linux regression timeout for very slow configs 2019-04-21 22:16:42 +02:00
Charles Papon 633e057d11 Split machine os regression in two smaller parts 2019-04-21 20:30:58 +02:00
Charles Papon 14efe6ffda Riscv software model now implement interrupt priority accordingly to 496c59d064 (diff-a38d447c5232bd448697af4c6c8adb1a) changes 2019-04-21 20:01:39 +02:00
Charles Papon d7ca153c8b remove interrupt assertion 2019-04-21 19:45:24 +02:00
Charles Papon 0e10c460c3 Update Zephyr tests, the mem_pool_threadsafe one was bugy by the past, and now it is just too long 2019-04-21 17:58:42 +02:00
Charles Papon 4cbb93cfc8 Look like zephyr mem_pool_threadsafe is a broken test 2019-04-21 17:48:08 +02:00
Dolu1990 1c86bf7514 Increase liveness trigger to allow large instruction cache flush 2019-04-21 15:25:39 +02:00
Charles Papon 4efa3b0d45 Update readme 2019-04-21 14:41:27 +02:00
Dolu1990 d18dcc0540
Update regression.mk
reduce linux regression time a bit
2019-04-21 13:49:05 +02:00
Dolu1990 fc4c078f17
Update regression.mk
Reduce machine os time
2019-04-21 13:36:25 +02:00
Charles Papon 7e91b5e446 Fix travis 2019-04-21 12:55:01 +02:00
Charles Papon 963805ad48 Bring freertos back in tests
Better travis test range
2019-04-21 12:50:28 +02:00
Charles Papon edde3e3011 Add zephyr tests 2019-04-21 02:56:44 +02:00
Charles Papon 5cd74d2845 Merge remote-tracking branch 'origin/linuxDev' into linux 2019-04-20 15:33:30 +02:00
Charles Papon 3b0f2e9551 better travis timings
travis job naming
reduce verilator cache size
Fix dcache test timeout
travis cleaning
travis wip
verilator wip
fix java 10 compilation
Travis wip
travis rework
2019-04-20 14:56:56 +02:00
Charles Papon 06e63252e4 Merge branch 'linux' into linuxDev 2019-04-19 21:12:35 +02:00
Charles Papon b49076ecab add missing coremark patch 2019-04-19 19:41:05 +02:00
Charles Papon ac5517f199 Travis : Bring back random regressions 2019-04-19 18:33:04 +02:00
Charles Papon 728a5ff20f Fix coremark binaries (no csr) 2019-04-19 18:28:46 +02:00
Charles Papon a496638c72 fix travis 2019-04-19 17:38:51 +02:00
Charles Papon e47b76fa67 #60 Added automated linux regression in travis
Fix DBusCached plugin access sharing for the MMU deadlock when exception is in the decode stage
Fix IBusSimplePlugin issues with used with non regular configs + MMU
Bring back the LinuxGen config into a light one
2019-04-19 17:35:48 +02:00