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VexRiscv
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734 Commits 39 Branches 2 Tags 15 MiB
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734 Commits

Author SHA1 Message Date
Charles Papon 2810ff05b0 Fix emulator instruction emulation trap redirection to supervisor. 
Impact only AMO less configs
 2019-04-19 02:31:39 +02:00
Charles Papon b79b02152b #60 Fix SFENCE_VMA deadlock 2019-04-18 18:33:06 +02:00
Dolu1990 d2b324e32b Add jtag and vhdl option 2019-04-15 11:01:51 +02:00
Charles Papon 6f04c02cd2 TestInduvidualFeatures now use the linux config + MMU 2019-04-14 23:06:04 +02:00
Charles Papon 8c7407967e Fix non RVC fetcher exception PC capture 2019-04-14 23:04:30 +02:00
Charles Papon 61d25e931e #60 Add sim error message on RVC instruction without RVC capabilities 2019-04-13 10:44:06 +02:00
Charles Papon 5d1ec604b2 Make regression sim great again 2019-04-13 10:41:15 +02:00
Charles Papon 9ac1d3d59e riscv software model without RVC now trap on RVC instruction before pcWrite + 2 2019-04-13 10:40:53 +02:00
Charles Papon a12ca43284 README.md Update eclipse install 2019-04-12 17:41:15 +02:00
Charles Papon 3301a1b364 Add CsrPlugin.userGen option which now remove privilegeReg when not set 2019-04-12 16:37:34 +02:00
Charles Papon d5723968da Merge remote-tracking branch 'origin/master' into linux 
# Conflicts:
#	src/main/scala/vexriscv/plugin/IBusSimplePlugin.scala
#	src/test/cpp/regression/main.cpp
 2019-04-12 16:26:08 +02:00
Charles Papon 8421328ee1 restore freertos tests 2019-04-12 16:09:20 +02:00
Charles Papon 13b774b535 #69 Relax address calculation of decode branch predictor by adding KEEP synthesis attribut 2019-04-12 15:56:22 +02:00
Charles Papon 41ff87f83b Remove jalr from decode branch prediction missaligned inibition 2019-04-12 15:27:10 +02:00
Charles Papon 63cd5f42af Fix #69 discoverd fmax issue with decode stage branch predictions 2019-04-12 15:24:33 +02:00
Dolu1990 fdd2194c8f
Merge pull request #69 from tomverbeure/micro_warnings 
GenMicro with warnings
 2019-04-12 14:58:17 +02:00
Charles Papon b329ee85ad #60 Fix missing ecallGen flag 2019-04-11 15:30:54 +02:00
Charles Papon ece1e73547 Default linux config is now without RVC 
Remove all linux usless CSR from the config
Remove verilator instruction fetch check
 2019-04-11 01:18:15 +02:00
Charles Papon caa37a8028 Reduce machine mode emulator CSR requirements and emulate more CSR (in the case they aren't supporter in hardware) 2019-04-10 19:04:52 +02:00
Charles Papon 6b22594961 Flush MMU line with exception on context switching instead than on cmd fire 2019-04-10 15:42:39 +02:00
Charles Papon 926b74a203 shorter coremark 2019-04-10 15:41:58 +02:00
Charles Papon 189cadfbb3 Add coremark 2019-04-10 15:41:38 +02:00
Charles Papon d7f6c18c0a Fix DebugPlugin -> force machine mode, force uncached memory load 2019-04-10 00:35:15 +02:00
Charles Papon 9b6b65b8b4 Fix icache test when dynamic target branch prediction is enabled 2019-04-09 19:37:18 +02:00
Charles Papon a6dc530441 Added lrsc/amo tests 2019-04-09 19:27:42 +02:00
Charles Papon fd42e7701e Add hardware AMO, require AMO=yes in sim and withAmo=true in linux.scala 2019-04-09 01:22:32 +02:00
Charles Papon 21cb8615fd Clean and fix things to get all the non-linux configs and machine only configs working 2019-04-08 16:06:05 +02:00
Charles Papon 32921491b8 #60 Fix instruction cache refill 2019-04-08 14:24:37 +02:00
Charles Papon fd15a938c5 #60 Fix machine mode emulator atomic emulation. Do not write regfile if the page was set as read only. 2019-04-08 13:20:56 +02:00
Charles Papon c2595273ec Add a busy flag from MMU ports 
iBus/dBus now halt on MMU busy, which avoid looping forever on page fault
 2019-04-08 11:38:40 +02:00
Charles Papon f89ee0d422 #60 Fix MMU holding invalid tlb, while linux is assuming it isn't doing so. 2019-04-07 15:44:25 +02:00
Tom Verbeure 4fd36454d7 Complain about wrong earlyBranch settings. 2019-04-06 12:58:19 -07:00
Tom Verbeure 39a4aa5e26 GenMicroNoCsr: no memory stage, no write-back stage 2019-04-06 12:38:54 -07:00
Charles Papon ffafc27104 Merge branch 'linuxDev' into linux 2019-04-06 02:01:08 +02:00
Charles Papon 6df3e57843 workaround Verilator comparaison linting 2019-04-06 02:00:47 +02:00
Charles Papon 21b4ae8f2f update todo, nothing todo ? everything done ? 2019-04-06 01:42:01 +02:00
Charles Papon e7f3dd5553 Rework CsrPlugin exception delegation 2019-04-05 23:40:39 +02:00
Charles Papon ddf0f06834 Add more delegation tests 
Reduce dcache test duration
 2019-04-05 22:56:12 +02:00
Charles Papon acaa931e11 Rework CsrPlugin interrupt delegation 2019-04-05 22:55:42 +02:00
Charles Papon 9e72971ff0 Move user mode page fault checkes from iBus/dBus plugin into the MmuPlugin 
SUM was in fact already supported
 2019-04-05 21:34:44 +02:00
Charles Papon 82c894932a update todolist 2019-04-05 20:04:28 +02:00
Charles Papon aeb418a99e Add dcache tests 2019-04-05 20:03:22 +02:00
Charles Papon 5a6665e57f Fix DataCache flush on the last line 2019-04-05 20:02:57 +02:00
Charles Papon 8459d423b8 add icache flush test 2019-04-05 18:11:33 +02:00
Charles Papon 60a41bfc75 rework i$ flush 2019-04-05 18:11:10 +02:00
Charles Papon f5d4e745c7 Look like precise fence.i isn't required in practice 2019-04-05 18:08:25 +02:00
Charles Papon 446e9625af Centralised all todo in linux.scala 
Sorted out fence fence.i instruction in iBus/dBus plugins.
Fixed MMU permitions while in used mode and bypassing the MMU
 2019-04-05 12:17:29 +02:00
Charles Papon 888e1c0b8a Fix RVC instruction cache xtval allignement 2019-04-05 01:08:57 +02:00
Charles Papon 8e6010fd71 Got the debug plugin working with the linux config (had to disable CSR ebreak) 2019-04-05 00:25:27 +02:00
Charles Papon 4f0a02594c Change LR/SC to reserve the whole memory 
Fix MPP access from other plugins
Got all the common configuration to compile and pass regression excepted the debugger one
First synthesis results
 2019-04-04 20:34:35 +02:00